From 4620f4c5aaba29f4fa7dc06a50c1355e2e193e62 Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Tue, 10 Mar 2009 21:02:44 +0000 Subject: [PATCH] cleaned up some code (knocked off 100+ lines in Alloc.inl), and implemented 'ESUM' opcode. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cotton2: write more helpful logs kthx ;p doesn't matter, no-one cares what i write since it doesn't effect anything for now cotton, stop posting those useless commit comments XD no no, please continue. they're fun, i look forward to read them from time to time :°D lol :D Please spend more time making them more amusing. cotton2: it does matter dwarg: yeah i know! drk||Raz: Why? They're useless for reversion testing i have to think of good stuff to write :O when the next vu coders (if any, ever ;p) want to look at your code .. and the history is full of crap that won't be much useful ;p there won't be a next vu coder! Comments in the actual code would be more useful, wouldn't they? my code is perfect! lol >.> <.< but seriously i don't think it can get better unless like Rather than going back and comparing SVN comments to changes made way back when you want to support AVX or w/e intel's new SSE thing is called and anyway AVX is like 3 years away in that timeline pcsx2 i think will be stabilized :°D yeah cotton2: just log kthx implemented y,x,z :> thats what the diffs are for! and anyway really its useless for this stage yea i know until microVU is active and used by PCSX2 i'm just implementing different opcodes though, its not like i'm chaning features you can tell anything from the code -- no comments or changelog needed.Right ? ;p then every change should be documented for regression testing drk: yup! well its not like i'm changing stuff i'm just implementing things that havn't been coded so theres nothing to regress to yep git-svn-id: http://pcsx2.googlecode.com/svn/trunk@742 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/microVU_Alloc.inl | 293 ++++++++++-------------------------- pcsx2/x86/microVU_Lower.inl | 15 +- pcsx2/x86/microVU_Upper.inl | 51 ++++--- 3 files changed, 118 insertions(+), 241 deletions(-) diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index af260661be..b2ff61451d 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -36,14 +36,14 @@ if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, _X_Y_Z_W); \ } -#define getZeroSS(reg) { \ +#define getZero(reg) { \ if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \ else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } -#define getZero(reg) { \ - if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \ - else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ +#define getReg6(reg, _reg_) { \ + if (!_reg_) { getZero(reg); } \ + else { getReg(reg, _reg_); } \ } microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) { @@ -51,26 +51,9 @@ microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; - if (_XYZW_SS) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - - if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZeroSS(Ft); } - else { getReg(Ft, _Ft_); } - } - } - else { - if (!_Fs_) { getZero(Fs); } - else { getReg(Fs, _Fs_); } - - if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZero(Ft); } - else { getReg(Ft, _Ft_); } - } - } + getReg6(Fs, _Fs_); + if (_Ft_ == _Fs_) { Ft = Fs; } + else { getReg6(Ft, _Ft_); } } microVUt(void) mVUallocFMAC1b(int& Fd) { @@ -88,14 +71,7 @@ microVUt(void) mVUallocFMAC2a(int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFs; - if (_XYZW_SS) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero(Fs); } - else { getReg(Fs, _Fs_); } - } + getReg6(Fs, _Fs_); } microVUt(void) mVUallocFMAC2b(int& Ft) { @@ -139,21 +115,15 @@ microVUt(void) mVUallocFMAC3a(int& Fd, int& Fs, int& Ft) { Ft = xmmFt; Fd = xmmFs; if (_XYZW_SS) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - + getReg6(Fs, _Fs_); if ( (_Ft_ == _Fs_) && ((_X && _bc_x) || (_Y && _bc_y) || (_Z && _bc_w) || (_W && _bc_w)) ) { Ft = Fs; } - else { - if (!_Ft_) { getZero3SS(Ft); } - else { getReg3SS(Ft, _Ft_); } - } + else if (!_Ft_) { getZero3SS(Ft); } + else { getReg3SS(Ft, _Ft_); } } else { - if (!_Fs_) { getZero(Fs); } - else { getReg(Fs, _Fs_); } - + getReg6(Fs, _Fs_); if (!_Ft_) { getZero3(Ft); } else { getReg3(Ft, _Ft_); } } @@ -188,24 +158,17 @@ microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) { Ft = xmmFt; getACC(ACC); if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - + getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZeroSS(Ft); } - else { getReg(Ft, _Ft_); } - } + else { getReg6(Ft, _Ft_); } } else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } + if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZero4(Ft); } - else { getReg4(Ft, _Ft_); } - } + else if (!_Ft_) { getZero4(Ft); } + else { getReg4(Ft, _Ft_); } } } @@ -225,16 +188,10 @@ microVUt(void) mVUallocFMAC5a(int& ACC, int& Fs, int& Ft) { Ft = xmmFt; getACC(ACC); if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - - if ( (_Ft_ == _Fs_) && _bc_x) { - Ft = Fs; - } - else { - if (!_Ft_) { getZero3SS(Ft); } - else { getReg3SS(Ft, _Ft_); } - } + getReg6(Fs, _Fs_); + if ((_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } + else if (!_Ft_) { getZero3SS(Ft); } + else { getReg3SS(Ft, _Ft_); } } else { if (!_Fs_) { getZero4(Fs); } @@ -266,14 +223,7 @@ microVUt(void) mVUallocFMAC6a(int& Fd, int& Fs, int& Ft) { Ft = xmmFt; Fd = xmmFs; getIreg(Ft); - if (_XYZW_SS) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero(Fs); } - else { getReg(Fs, _Fs_); } - } + getReg6(Fs, _Fs_); } microVUt(void) mVUallocFMAC6b(int& Fd) { @@ -290,14 +240,9 @@ microVUt(void) mVUallocFMAC7a(int& ACC, int& Fs, int& Ft) { Ft = xmmFt; getACC(ACC); getIreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC7b(int& ACC, int& Fs) { @@ -315,24 +260,17 @@ microVUt(void) mVUallocFMAC8a(int& Fd, int&ACC, int& Fs, int& Ft) { Fd = xmmFs; ACC = xmmACC0 + readACC; if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - + getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZeroSS(Ft); } - else { getReg(Ft, _Ft_); } - } + else { getReg6(Ft, _Ft_); } } else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } + if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZero4(Ft); } - else { getReg4(Ft, _Ft_); } - } + else if (!_Ft_) { getZero4(Ft); } + else { getReg4(Ft, _Ft_); } } } @@ -355,24 +293,17 @@ microVUt(void) mVUallocFMAC9a(int& Fd, int&ACC, int& Fs, int& Ft) { ACC = xmmT1; SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - + getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZeroSS(Ft); } - else { getReg(Ft, _Ft_); } - } + else { getReg6(Ft, _Ft_); } } else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } + if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZero4(Ft); } - else { getReg4(Ft, _Ft_); } - } + else if (!_Ft_) { getZero4(Ft); } + else { getReg4(Ft, _Ft_); } } } @@ -394,16 +325,10 @@ microVUt(void) mVUallocFMAC10a(int& Fd, int& ACC, int& Fs, int& Ft) { Fd = xmmFs; ACC = xmmACC0 + readACC; if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - - if ( (_Ft_ == _Fs_) && _bc_x) { - Ft = Fs; - } - else { - if (!_Ft_) { getZero3SS(Ft); } - else { getReg3SS(Ft, _Ft_); } - } + getReg6(Fs, _Fs_); + if ( (_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } + else if (!_Ft_) { getZero3SS(Ft); } + else { getReg3SS(Ft, _Ft_); } } else { if (!_Fs_) { getZero4(Fs); } @@ -430,16 +355,10 @@ microVUt(void) mVUallocFMAC11a(int& Fd, int& ACC, int& Fs, int& Ft) { ACC = xmmT1; SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - - if ( (_Ft_ == _Fs_) && _bc_x) { - Ft = Fs; - } - else { - if (!_Ft_) { getZero3SS(Ft); } - else { getReg3SS(Ft, _Ft_); } - } + getReg6(Fs, _Fs_); + if ( (_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } + else if (!_Ft_) { getZero3SS(Ft); } + else { getReg3SS(Ft, _Ft_); } } else { if (!_Fs_) { getZero4(Fs); } @@ -465,14 +384,9 @@ microVUt(void) mVUallocFMAC12a(int& Fd, int&ACC, int& Fs, int& Ft) { Fd = xmmFs; ACC = xmmACC0 + readACC; getIreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC12b(int& Fd) { @@ -491,14 +405,9 @@ microVUt(void) mVUallocFMAC13a(int& Fd, int&ACC, int& Fs, int& Ft) { ACC = xmmT1; SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); getIreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC13b(int& Fd) { @@ -516,24 +425,17 @@ microVUt(void) mVUallocFMAC14a(int& ACCw, int&ACCr, int& Fs, int& Ft) { Ft = xmmFt; ACCr = xmmACC0 + readACC; if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - + getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZeroSS(Ft); } - else { getReg(Ft, _Ft_); } - } + else { getReg6(Ft, _Ft_); } } else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } + if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } if (_Ft_ == _Fs_) { Ft = Fs; } - else { - if (!_Ft_) { getZero4(Ft); } - else { getReg4(Ft, _Ft_); } - } + else if (!_Ft_) { getZero4(Ft); } + else { getReg4(Ft, _Ft_); } } } @@ -570,16 +472,10 @@ microVUt(void) mVUallocFMAC16a(int& ACCw, int&ACCr, int& Fs, int& Ft) { Ft = xmmFt; ACCr = xmmACC0 + readACC; if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - - if ( (_Ft_ == _Fs_) && _bc_x) { - Ft = Fs; - } - else { - if (!_Ft_) { getZero3SS(Ft); } - else { getReg3SS(Ft, _Ft_); } - } + getReg6(Fs, _Fs_); + if ((_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } + else if (!_Ft_) { getZero3SS(Ft); } + else { getReg3SS(Ft, _Ft_); } } else { if (!_Fs_) { getZero4(Fs); } @@ -669,14 +565,9 @@ microVUt(void) mVUallocFMAC20a(int& ACCw, int&ACCr, int& Fs, int& Ft) { Ft = xmmFt; ACCr = xmmACC0 + readACC; getIreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC20b(int& ACCw, int& Fs) { @@ -712,14 +603,7 @@ microVUt(void) mVUallocFMAC22a(int& Fd, int& Fs, int& Ft) { Ft = xmmFt; Fd = xmmFs; getQreg(Ft); - if (_XYZW_SS) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero(Fs); } - else { getReg(Fs, _Fs_); } - } + getReg6(Fs, _Fs_); } microVUt(void) mVUallocFMAC22b(int& Fd) { @@ -736,21 +620,15 @@ microVUt(void) mVUallocFMAC23a(int& ACC, int& Fs, int& Ft) { Ft = xmmFt; getACC(ACC); getQreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC23b(int& ACC, int& Fs) { mVUallocFMAC4b(ACC, Fs); } - //------------------------------------------------------------------ // FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) //------------------------------------------------------------------ @@ -762,14 +640,9 @@ microVUt(void) mVUallocFMAC24a(int& Fd, int&ACC, int& Fs, int& Ft) { Fd = xmmFs; ACC = xmmACC0 + readACC; getQreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC24b(int& Fd) { @@ -788,14 +661,9 @@ microVUt(void) mVUallocFMAC25a(int& Fd, int&ACC, int& Fs, int& Ft) { ACC = xmmT1; SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); getQreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC25b(int& Fd) { @@ -813,14 +681,9 @@ microVUt(void) mVUallocFMAC26a(int& ACCw, int&ACCr, int& Fs, int& Ft) { Ft = xmmFt; ACCr = xmmACC0 + readACC; getQreg(Ft); - if (_XYZW_SS && _X) { - if (!_Fs_) { getZeroSS(Fs); } - else { getReg(Fs, _Fs_); } - } - else { - if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } - } + if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } microVUt(void) mVUallocFMAC26b(int& ACCw, int& Fs) { diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index 43ae6e8d80..5ff2a4b495 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -217,7 +217,20 @@ microVUf(void) mVU_ERSQRT() {} microVUf(void) mVU_ESADD() {} microVUf(void) mVU_ESIN() {} microVUf(void) mVU_ESQRT() {} -microVUf(void) mVU_ESUM() {} +microVUf(void) mVU_ESUM() { + microVU* mVU = mVUx; + if (recPass == 0) {} + else { + getReg6(xmmFs, _Fs_); + SSE_SHUFPS_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance + SSE2_PSHUFD_XMM_to_XMM(xmmFt, xmmFs, 0x1b); + SSE_ADDPS_XMM_to_XMM(xmmFs, xmmFt); + SSE2_PSHUFD_XMM_to_XMM(xmmFt, xmmFs, 0x01); + SSE_ADDSS_XMM_to_XMM(xmmFs, xmmFt); + SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); + SSE_SHUFPS_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back + } +} microVUf(void) mVU_FCAND() {} microVUf(void) mVU_FCEQ() {} diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index 9b5e3a5090..f0336aa081 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -78,6 +78,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // Helper Macros //------------------------------------------------------------------ +// FMAC1 - Normal FMAC Opcodes #define mVU_FMAC1(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -91,7 +92,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC1b(Fd); \ } \ } - +// FMAC3 - BC(xyzw) FMAC Opcodes #define mVU_FMAC3(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -105,7 +106,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC3b(Fd); \ } \ } - +// FMAC4 - FMAC Opcodes Storing Result to ACC #define mVU_FMAC4(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -119,7 +120,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC4b(ACC, Fs); \ } \ } - +// FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC #define mVU_FMAC5(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -133,7 +134,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC5b(ACC, Fs); \ } \ } - +// FMAC6 - Normal FMAC Opcodes (I Reg) #define mVU_FMAC6(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -147,7 +148,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC6b(Fd); \ } \ } - +// FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg) #define mVU_FMAC7(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -161,7 +162,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC7b(ACC, Fs); \ } \ } - +// FMAC8 - MADD FMAC Opcode Storing Result to Fd #define mVU_FMAC8(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -181,7 +182,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC8b(Fd); \ } \ } - +// FMAC9 - MSUB FMAC Opcode Storing Result to Fd #define mVU_FMAC9(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -201,7 +202,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC9b(Fd); \ } \ } - +// FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd #define mVU_FMAC10(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -221,7 +222,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC10b(Fd); \ } \ } - +// FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd #define mVU_FMAC11(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -241,7 +242,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC11b(Fd); \ } \ } - +// FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg) #define mVU_FMAC12(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -261,7 +262,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC12b(Fd); \ } \ } - +// FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg) #define mVU_FMAC13(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -281,7 +282,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC13b(Fd); \ } \ } - +// FMAC14 - MADDA FMAC Opcode #define mVU_FMAC14(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -301,7 +302,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC14b(ACCw, Fs); \ } \ } - +// FMAC15 - MSUBA FMAC Opcode #define mVU_FMAC15(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -321,7 +322,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC15b(ACCw, ACCr); \ } \ } - +// FMAC16 - MADDA BC(xyzw) FMAC Opcode #define mVU_FMAC16(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -341,7 +342,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC16b(ACCw, Fs); \ } \ } - +// FMAC17 - MSUBA BC(xyzw) FMAC Opcode #define mVU_FMAC17(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -361,7 +362,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC17b(ACCw, ACCr); \ } \ } - +// FMAC18 - OPMULA FMAC Opcode #define mVU_FMAC18(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -374,7 +375,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC18b(ACC, Fs); \ } \ } - +// FMAC19 - OPMULA FMAC Opcode #define mVU_FMAC19(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -388,7 +389,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC19b(Fd); \ } \ } - +// FMAC20 - MADDA FMAC Opcode (I Reg) #define mVU_FMAC20(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -408,7 +409,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC20b(ACCw, Fs); \ } \ } - +// FMAC21 - MSUBA FMAC Opcode (I Reg) #define mVU_FMAC21(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -428,7 +429,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC21b(ACCw, ACCr); \ } \ } - +// FMAC22 - Normal FMAC Opcodes (Q Reg) #define mVU_FMAC22(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -442,7 +443,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC22b(Fd); \ } \ } - +// FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg) #define mVU_FMAC23(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -456,7 +457,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC23b(ACC, Fs); \ } \ } - +// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) #define mVU_FMAC24(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -476,7 +477,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC24b(Fd); \ } \ } - +// FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg) #define mVU_FMAC25(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -496,7 +497,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC25b(Fd); \ } \ } - +// FMAC26 - MADDA FMAC Opcode (Q Reg) #define mVU_FMAC26(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ @@ -516,7 +517,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC26b(ACCw, Fs); \ } \ } - +// FMAC27 - MSUBA FMAC Opcode (Q Reg) #define mVU_FMAC27(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \