mirror of https://github.com/PCSX2/pcsx2.git
EE: freeMMXreg is a nop because inuse == 0
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6f561d6bd7
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@ -313,10 +313,8 @@ struct _mmxregs {
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void _initMMXregs();
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void _initMMXregs();
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void _clearNeededMMXregs();
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void _clearNeededMMXregs();
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void _freeMMXreg(u32 mmxreg);
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void _flushMMXregs();
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void _flushMMXregs();
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u8 _hasFreeMMXreg();
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u8 _hasFreeMMXreg();
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void _freeMMXregs();
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int _getNumMMXwrite();
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int _getNumMMXwrite();
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// returns new index of reg, lower 32 bits already in mmx
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// returns new index of reg, lower 32 bits already in mmx
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@ -519,30 +519,6 @@ int _getNumMMXwrite()
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return num;
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return num;
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}
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}
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void _freeMMXreg(u32 mmxreg)
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{
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pxAssert( mmxreg < iREGCNT_MMX );
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if (!mmxregs[mmxreg].inuse) return;
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if (mmxregs[mmxreg].mode & MODE_WRITE ) {
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// Not sure if this line is accurate, since if the 32 was 34, it would be MMX_ISGPR.
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if ( /*mmxregs[mmxreg].reg >= MMX_GPR &&*/ mmxregs[mmxreg].reg < MMX_GPR+32 ) // Checking if a u32 is >=0 is pointless.
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pxAssert( !(g_cpuHasConstReg & (1<<(mmxregs[mmxreg].reg-MMX_GPR))) );
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pxAssert( mmxregs[mmxreg].reg != MMX_GPR );
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if( MMX_IS32BITS(mmxregs[mmxreg].reg) )
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xMOVD(ptr[(_MMXGetAddr(mmxregs[mmxreg].reg))], xRegisterMMX(mmxreg));
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else
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xMOVQ(ptr[(_MMXGetAddr(mmxregs[mmxreg].reg))], xRegisterMMX(mmxreg));
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SetMMXstate();
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}
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mmxregs[mmxreg].mode &= ~MODE_WRITE;
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mmxregs[mmxreg].inuse = 0;
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}
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// write all active regs
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// write all active regs
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void _flushMMXregs()
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void _flushMMXregs()
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{
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{
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@ -569,23 +545,7 @@ void _flushMMXregs()
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}
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}
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}
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}
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void _freeMMXregs()
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{
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uint i;
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for (i=0; i<iREGCNT_MMX; i++) {
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if (mmxregs[i].inuse == 0) continue;
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pxAssert( mmxregs[i].reg != MMX_TEMP );
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pxAssert( mmxregs[i].mode & MODE_READ );
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_freeMMXreg(i);
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}
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}
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void SetFPUstate() {
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void SetFPUstate() {
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_freeMMXreg(6);
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_freeMMXreg(7);
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if (x86FpuState == MMX_STATE) {
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if (x86FpuState == MMX_STATE) {
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xEMMS();
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xEMMS();
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x86FpuState = FPU_STATE;
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x86FpuState = FPU_STATE;
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@ -961,9 +961,7 @@ void iFlushCall(int flushtype)
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else if( flushtype & FLUSH_FLUSH_XMM)
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else if( flushtype & FLUSH_FLUSH_XMM)
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_flushXMMregs();
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_flushXMMregs();
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if( flushtype & FLUSH_FREE_MMX )
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if( flushtype & FLUSH_FLUSH_MMX)
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_freeMMXregs();
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else if( flushtype & FLUSH_FLUSH_MMX)
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_flushMMXregs();
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_flushMMXregs();
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if( flushtype & FLUSH_CACHED_REGS )
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if( flushtype & FLUSH_CACHED_REGS )
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@ -1344,7 +1342,6 @@ void recompileNextInstruction(int delayslot)
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#if 0
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#if 0
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// TODO: Free register ?
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// TODO: Free register ?
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// _freeXMMregs();
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// _freeXMMregs();
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// _freeMMXregs();
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#endif
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#endif
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}
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}
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}
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}
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@ -1369,7 +1366,6 @@ void recompileNextInstruction(int delayslot)
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_clearNeededXMMregs();
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_clearNeededXMMregs();
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// _freeXMMregs();
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// _freeXMMregs();
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// _freeMMXregs();
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// _flushCachedRegs();
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// _flushCachedRegs();
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// g_cpuHasConstReg = 1;
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// g_cpuHasConstReg = 1;
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@ -17,7 +17,6 @@
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#define REC_VUOP(VU, f) { \
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#define REC_VUOP(VU, f) { \
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_freeXMMregs(/*&VU*/); \
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_freeXMMregs(/*&VU*/); \
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_freeMMXregs(); \
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SetFPUstate();) \
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SetFPUstate();) \
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xMOV(ptr32[&VU.code], (u32)VU.code); \
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xMOV(ptr32[&VU.code], (u32)VU.code); \
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xCALL((void*)(uptr)VU##MI_##f); \
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xCALL((void*)(uptr)VU##MI_##f); \
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@ -25,7 +24,6 @@
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#define REC_VUOPs(VU, f) { \
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#define REC_VUOPs(VU, f) { \
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_freeXMMregs(); \
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_freeXMMregs(); \
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_freeMMXregs(); \
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SetFPUstate();) \
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SetFPUstate();) \
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if (VU==&VU1) { \
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if (VU==&VU1) { \
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xMOV(ptr32[&VU1.code], (u32)VU1.code); \
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xMOV(ptr32[&VU1.code], (u32)VU1.code); \
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@ -39,7 +37,6 @@
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#define REC_VUOPFLAGS(VU, f) { \
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#define REC_VUOPFLAGS(VU, f) { \
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_freeXMMregs(/*&VU*/); \
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_freeXMMregs(/*&VU*/); \
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_freeMMXregs(); \
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SetFPUstate(); \
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SetFPUstate(); \
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xMOV(ptr32[&VU.code], (u32)VU.code); \
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xMOV(ptr32[&VU.code], (u32)VU.code); \
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xCALL((void*)(uptr)VU##MI_##f); \
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xCALL((void*)(uptr)VU##MI_##f); \
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@ -47,7 +44,6 @@
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#define REC_VUBRANCH(VU, f) { \
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#define REC_VUBRANCH(VU, f) { \
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_freeXMMregs(/*&VU*/); \
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_freeXMMregs(/*&VU*/); \
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_freeMMXregs(); \
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SetFPUstate(); \
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SetFPUstate(); \
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xMOV(ptr32[&VU.code], (u32)VU.code); \
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xMOV(ptr32[&VU.code], (u32)VU.code); \
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xMOV(ptr32[&VU.VI[REG_TPC].UL], (u32)pc); \
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xMOV(ptr32[&VU.VI[REG_TPC].UL], (u32)pc); \
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