diff --git a/pcsx2/x86/iCore.h b/pcsx2/x86/iCore.h
index d99cc2980f..4df9ba0403 100644
--- a/pcsx2/x86/iCore.h
+++ b/pcsx2/x86/iCore.h
@@ -313,10 +313,8 @@ struct _mmxregs {
 
 void _initMMXregs();
 void _clearNeededMMXregs();
-void _freeMMXreg(u32 mmxreg);
 void _flushMMXregs();
 u8 _hasFreeMMXreg();
-void _freeMMXregs();
 int _getNumMMXwrite();
 
 // returns new index of reg, lower 32 bits already in mmx
diff --git a/pcsx2/x86/ix86-32/iCore-32.cpp b/pcsx2/x86/ix86-32/iCore-32.cpp
index 98acbdddcb..57b9f8c4c0 100644
--- a/pcsx2/x86/ix86-32/iCore-32.cpp
+++ b/pcsx2/x86/ix86-32/iCore-32.cpp
@@ -519,30 +519,6 @@ int _getNumMMXwrite()
 	return num;
 }
 
-void _freeMMXreg(u32 mmxreg)
-{
-	pxAssert( mmxreg < iREGCNT_MMX );
-	if (!mmxregs[mmxreg].inuse) return;
-
-	if (mmxregs[mmxreg].mode & MODE_WRITE ) {
-		// Not sure if this line is accurate, since if the 32 was 34, it would be MMX_ISGPR.
-		if ( /*mmxregs[mmxreg].reg >= MMX_GPR &&*/ mmxregs[mmxreg].reg < MMX_GPR+32 ) // Checking if a u32 is >=0 is pointless.
-			pxAssert( !(g_cpuHasConstReg & (1<<(mmxregs[mmxreg].reg-MMX_GPR))) );
-
-		pxAssert( mmxregs[mmxreg].reg != MMX_GPR );
-
-		if( MMX_IS32BITS(mmxregs[mmxreg].reg) )
-			xMOVD(ptr[(_MMXGetAddr(mmxregs[mmxreg].reg))], xRegisterMMX(mmxreg));
-		else
-			xMOVQ(ptr[(_MMXGetAddr(mmxregs[mmxreg].reg))], xRegisterMMX(mmxreg));
-
-		SetMMXstate();
-	}
-
-	mmxregs[mmxreg].mode &= ~MODE_WRITE;
-	mmxregs[mmxreg].inuse = 0;
-}
-
 // write all active regs
 void _flushMMXregs()
 {
@@ -569,23 +545,7 @@ void _flushMMXregs()
 	}
 }
 
-void _freeMMXregs()
-{
-	uint i;
-	for (i=0; i<iREGCNT_MMX; i++) {
-		if (mmxregs[i].inuse == 0) continue;
-
-		pxAssert( mmxregs[i].reg != MMX_TEMP );
-		pxAssert( mmxregs[i].mode & MODE_READ );
-
-		_freeMMXreg(i);
-	}
-}
-
 void SetFPUstate() {
-	_freeMMXreg(6);
-	_freeMMXreg(7);
-
 	if (x86FpuState == MMX_STATE) {
 		xEMMS();
 		x86FpuState = FPU_STATE;
diff --git a/pcsx2/x86/ix86-32/iR5900-32.cpp b/pcsx2/x86/ix86-32/iR5900-32.cpp
index 1b02f60389..adacbaa47a 100644
--- a/pcsx2/x86/ix86-32/iR5900-32.cpp
+++ b/pcsx2/x86/ix86-32/iR5900-32.cpp
@@ -961,9 +961,7 @@ void iFlushCall(int flushtype)
 	else if( flushtype & FLUSH_FLUSH_XMM)
 		_flushXMMregs();
 
-	if( flushtype & FLUSH_FREE_MMX )
-		_freeMMXregs();
-	else if( flushtype & FLUSH_FLUSH_MMX)
+	if( flushtype & FLUSH_FLUSH_MMX)
 		_flushMMXregs();
 
 	if( flushtype & FLUSH_CACHED_REGS )
@@ -1344,7 +1342,6 @@ void recompileNextInstruction(int delayslot)
 #if 0
 			// TODO: Free register ?
 			//	_freeXMMregs();
-			//	_freeMMXregs();
 #endif
 		}
 	}
@@ -1369,7 +1366,6 @@ void recompileNextInstruction(int delayslot)
 	_clearNeededXMMregs();
 
 //	_freeXMMregs();
-//	_freeMMXregs();
 //	_flushCachedRegs();
 //	g_cpuHasConstReg = 1;
 
diff --git a/pcsx2/x86/sVU_Debug.h b/pcsx2/x86/sVU_Debug.h
index f91480f210..242c8f1a4c 100644
--- a/pcsx2/x86/sVU_Debug.h
+++ b/pcsx2/x86/sVU_Debug.h
@@ -17,7 +17,6 @@
 
 #define REC_VUOP(VU, f) { \
 	_freeXMMregs(/*&VU*/); \
-	_freeMMXregs(); \
 	SetFPUstate();) \
 	xMOV(ptr32[&VU.code], (u32)VU.code); \
 	xCALL((void*)(uptr)VU##MI_##f); \
@@ -25,7 +24,6 @@
 
 #define REC_VUOPs(VU, f) { \
 	_freeXMMregs(); \
-	_freeMMXregs(); \
 	SetFPUstate();) \
 	if (VU==&VU1) {  \
 		xMOV(ptr32[&VU1.code], (u32)VU1.code); \
@@ -39,7 +37,6 @@
 
 #define REC_VUOPFLAGS(VU, f) { \
 	_freeXMMregs(/*&VU*/); \
-	_freeMMXregs(); \
 	SetFPUstate(); \
 	xMOV(ptr32[&VU.code], (u32)VU.code); \
 	xCALL((void*)(uptr)VU##MI_##f); \
@@ -47,7 +44,6 @@
 
 #define REC_VUBRANCH(VU, f) { \
 	_freeXMMregs(/*&VU*/); \
-	_freeMMXregs(); \
 	SetFPUstate(); \
 	xMOV(ptr32[&VU.code], (u32)VU.code); \
 	xMOV(ptr32[&VU.VI[REG_TPC].UL], (u32)pc); \