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SPU2-X: 

- Ok, that interrupt commit in r2600 was silly. The "special register write" is a simple set audio to max volume. We don't interrupt those :p
NEW IOP DMAC:
- Make the adma interrupts happen early, as in the previous commit for old dmac.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2602 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2010-02-17 22:37:13 +00:00
parent f6119e02f0
commit 42cb1c4bb1
3 changed files with 22 additions and 7 deletions
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8
pcsx2/IopDma.cpp
View File

@ -512,7 +512,15 @@ static void __releaseinline IopDmaProcessChannel(int elapsed, int& MinDelay)
if (RequestedDelay != 0) NextUpdateDelay = RequestedDelay;
// SPU2 adma early interrupts. PCSX2 likes those better currently.
if((channel==4 || channel==7) && (ch->ByteCount<=0) && (ProcessedBytes <= 1024))
{
ch->NextUpdate = 0;
}
else
ch->NextUpdate += NextUpdateDelay;
//ch->NextUpdate += NextUpdateDelay;
}
}

2
plugins/spu2-x/src/ReadInput.cpp
View File

@ -90,6 +90,7 @@ StereoOut32 V_Core::ReadInput_HiFi()
}
}
InputDataLeft = 0;
// Hack, kinda. We call the interrupt early here, since PCSX2 doesn't like them delayed.
//DMAICounter = 1;
if(Index == 0) { if(dma4callback) dma4callback(); }
else { if(dma7callback) dma7callback(); }
@ -151,6 +152,7 @@ StereoOut32 V_Core::ReadInput()
}
InputDataLeft = 0;
// Hack, kinda. We call the interrupt early here, since PCSX2 doesn't like them delayed.
//DMAICounter = 1;
if(Index == 0) { if(dma4callback) dma4callback(); }
else { if(dma7callback) dma7callback(); }

17
plugins/spu2-x/src/spu2sys.cpp
View File

@ -1431,12 +1431,17 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
{
// Check for these 2 adresses and schedule an interrupt when they get written with 0x3fff.
// This is what peops spu2 does, and it helps silent hill origins start a bit more stuff.
if (value == 0x3fff && (rmem == 0x1f900500 || rmem == 0x1f900400) ) {
// no idea which core ><
Spdif.Info |= 4 << 0;
SetIrqCall();
ConLog( "SPU2-X: Schedule IRQ for odd register write. rmem = %x , value = %x \n", rmem, value);
}
// Update: 0x1f900400 is core0's volume register. Interrupting here is wrong.
// So SH:O just set the volume to max, which is a pretty normal operation anyway.
// Keeping this in for reference :p
//if (value == 0x3fff && (rmem == 0x1f900500 || rmem == 0x1f900400) ) {
// // no idea which core ><
// Spdif.Info |= 4 << 0;
// SetIrqCall();
// ConLog( "SPU2-X: Schedule IRQ for odd register write. rmem = %x , value = %x \n", rmem, value);
//}
tbl_reg_writes[(rmem&0x7ff)/2]( value );
}