mirror of https://github.com/PCSX2/pcsx2.git
Improved SSE detection:
* SSE3 detection via cpuid implemented. [fixes Linux -- the force_sse3 option should no longer be needed!] * Instruction tests are now done for SSE3, SSE4, and SSE4.1 to confirm cpuid results (I doubt this is necessary, but the old code did it for SSE3, so I figured I'd keep it and log results anytime an inconsistency is detected). * SSE4.2 and SSE4a detection added. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1086 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
6e82c77e92
commit
41079415fa
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@ -135,13 +135,15 @@ void SysDetect()
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"\t%sDetected SSE2\n"
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"\t%sDetected SSE3\n"
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"\t%sDetected SSSE3\n"
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"\t%sDetected SSE4.1\n", params
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"\t%sDetected SSE4.1\n"
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"\t%sDetected SSE4.2\n", params
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cpucaps.hasMultimediaExtensions ? "" : "Not ",
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cpucaps.hasStreamingSIMDExtensions ? "" : "Not ",
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cpucaps.hasStreamingSIMD2Extensions ? "" : "Not ",
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cpucaps.hasStreamingSIMD3Extensions ? "" : "Not ",
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cpucaps.hasSupplementalStreamingSIMD3Extensions ? "" : "Not ",
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cpucaps.hasStreamingSIMD4Extensions ? "" : "Not "
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cpucaps.hasStreamingSIMD4Extensions ? "" : "Not ",
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cpucaps.hasStreamingSIMD4Extensions2 ? "" : "Not "
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);
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if ( cpuinfo.x86ID[0] == 'A' ) //AMD cpu
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@ -150,10 +152,12 @@ void SysDetect()
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WriteLn(
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"\t%sDetected MMX2\n"
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"\t%sDetected 3DNOW\n"
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"\t%sDetected 3DNOW2\n", params
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"\t%sDetected 3DNOW2\n"
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"\t%sDetected SSE4a\n", params
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cpucaps.hasMultimediaExtensionsExt ? "" : "Not ",
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cpucaps.has3DNOWInstructionExtensions ? "" : "Not ",
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cpucaps.has3DNOWInstructionExtensionsExt ? "" : "Not "
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cpucaps.has3DNOWInstructionExtensionsExt ? "" : "Not ",
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cpucaps.hasStreamingSIMD4ExtensionsA ? "" : "Not "
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);
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}
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@ -23,6 +23,8 @@
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#include "RedtapeWindows.h"
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using namespace x86Emitter;
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#if defined (_MSC_VER) && _MSC_VER >= 1400
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extern "C"
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@ -148,31 +150,29 @@ u64 GetCPUTick( void )
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#endif
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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// Note: This function doesn't support GCC/Linux. Looking online it seems the only
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// way to simulate the Micrsoft SEH model is to use unix signals, and the 'sigaction'
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// function specifically. Maybe a project for a linux developer at a later date. :)
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void cpudetectSSE3(void* pfnCallSSE3)
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{
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cpucaps.hasStreamingSIMD3Extensions = 1;
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#ifdef _MSC_VER
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static bool _test_instruction( void* pfnCall )
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{
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__try {
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((void (*)())pfnCallSSE3)();
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((void (*)())pfnCall)();
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}
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__except(EXCEPTION_EXECUTE_HANDLER) {
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cpucaps.hasStreamingSIMD3Extensions = 0;
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return false;
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}
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#else // linux
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#ifdef PCSX2_FORCESSE3
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cpucaps.hasStreamingSIMD3Extensions = 1;
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#else
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// exception handling doesn't work, so disable for x86 builds of linux
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cpucaps.hasStreamingSIMD3Extensions = 0;
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#endif
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#endif
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return true;
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}
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static char* bool_to_char( bool testcond )
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{
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return testcond ? "true" : "false";
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}
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#endif
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#if defined __LINUX__
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#include <sys/time.h>
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@ -180,6 +180,8 @@ void cpudetectSSE3(void* pfnCallSSE3)
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#endif
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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s64 CPUSpeedHz( unsigned int time )
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{
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s64 timeStart,
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@ -197,9 +199,10 @@ s64 CPUSpeedHz( unsigned int time )
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timeStart = timeGetTime( );
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while( timeGetTime( ) == timeStart )
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{
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timeStart = timeGetTime( );
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}
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{
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timeStart = timeGetTime( );
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}
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for(;;)
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{
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timeStop = timeGetTime( );
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@ -294,6 +297,7 @@ void cpudetectInit()
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if ( iCpuId( 0x80000001, regs ) != -1 )
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{
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x86_64_12BITBRANDID = regs[1] & 0xfff;
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cpuinfo.x86EFlags2 = regs[ 2 ];
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cpuinfo.x86EFlags = regs[ 3 ];
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}
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@ -364,40 +368,85 @@ void cpudetectInit()
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cpucaps.hasMultiThreading = ( cpuinfo.x86Flags >> 28 ) & 1;
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cpucaps.hasThermalMonitor = ( cpuinfo.x86Flags >> 29 ) & 1;
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cpucaps.hasIntel64BitArchitecture = ( cpuinfo.x86Flags >> 30 ) & 1;
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//that is only for AMDs
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cpucaps.hasMultimediaExtensionsExt = ( cpuinfo.x86EFlags >> 22 ) & 1; //mmx2
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cpucaps.hasAMD64BitArchitecture = ( cpuinfo.x86EFlags >> 29 ) & 1; //64bit cpu
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cpucaps.has3DNOWInstructionExtensionsExt = ( cpuinfo.x86EFlags >> 30 ) & 1; //3dnow+
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cpucaps.has3DNOWInstructionExtensions = ( cpuinfo.x86EFlags >> 31 ) & 1; //3dnow
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cpucaps.hasStreamingSIMD4ExtensionsA = ( cpuinfo.x86EFlags2 >> 6 ) & 1; //INSERTQ / EXTRQ / MOVNT
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cpuinfo.cpuspeed = (u32)(CPUSpeedHz( 1000 ) / 1000000);
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// --> SSE 4.1 detection <--
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// We don't care about the small subset of CPUs using SSE4 (which is also hard to
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// detect, in addition to being of limited use due to the abbreviated instruction set).
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// So we'll just leave it at SSE 4.1. SSE4 cpu detection is ignored.
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cpuinfo.cpuspeed = (u32)(CPUSpeedHz( 600 ) / 1000000);
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cpucaps.hasStreamingSIMD4Extensions = ( cpuinfo.x86Flags2 >> 19 ) & 1; //sse4.1
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// --> SSSE3 detection <--
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// --> SSE3 / SSSE3 / SSE4.1 / SSE 4.2 detection <--
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cpucaps.hasStreamingSIMD3Extensions = ( cpuinfo.x86Flags2 >> 0 ) & 1; //sse3
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cpucaps.hasSupplementalStreamingSIMD3Extensions = ( cpuinfo.x86Flags2 >> 9 ) & 1; //ssse3
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cpucaps.hasStreamingSIMD4Extensions = ( cpuinfo.x86Flags2 >> 19 ) & 1; //sse4.1
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cpucaps.hasStreamingSIMD4Extensions2 = ( cpuinfo.x86Flags2 >> 20 ) & 1; //sse4.2
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// --> SSE3 detection <--
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// These instructions may not be recognized by some compilers, or may not have
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// intrinsic equivalents available. So we use our own ix86 emitter to generate
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// some code and run it that way. :)
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// Can the SSE3 / SSE4.1 bits be trusted? Using an instruction test is a very "complete"
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// approach to ensuring the bit is accurate, and at least one reported case of a Q9550 not
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// having SSE 4.1 set but still supporting it properly is fixed by this --air
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#ifdef _MSC_VER
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u8* recSSE = (u8*)HostSys::Mmap( NULL, 0x1000 );
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if( recSSE != NULL )
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{
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x86SetPtr(recSSE);
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SSE3_MOVSLDUP_XMM_to_XMM(XMM0, XMM0);
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xSetPtr( recSSE );
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xMOVSLDUP( xmm1, xmm0 );
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RET();
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cpudetectSSE3(recSSE);
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u8* funcSSSE3 = xGetPtr();
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xPABS.W( xmm0, xmm1 );
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RET();
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u8* funcSSE41 = xGetPtr();
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xBLEND.VPD( xmm1, xmm0 );
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RET();
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bool sse3_result = _test_instruction( recSSE ); // sse3
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bool ssse3_result = _test_instruction( funcSSSE3 );
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bool sse41_result = _test_instruction( funcSSE41 );
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HostSys::Munmap( recSSE, 0x1000 );
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// Test for and log any irregularities here.
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// We take the instruction test result over cpuid since (in theory) it should be a
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// more reliable gauge of the cpu's actual ability.
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if( sse3_result != cpucaps.hasStreamingSIMD3Extensions )
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{
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Console::Notice( "SSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
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params bool_to_char( cpucaps.hasStreamingSIMD3Extensions ), bool_to_char( sse3_result ) );
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cpucaps.hasStreamingSIMD3Extensions = sse3_result;
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}
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if( ssse3_result != cpucaps.hasSupplementalStreamingSIMD3Extensions )
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{
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Console::Notice( "SSSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
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params bool_to_char( cpucaps.hasSupplementalStreamingSIMD3Extensions ), bool_to_char( ssse3_result ) );
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cpucaps.hasSupplementalStreamingSIMD3Extensions = ssse3_result;
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}
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if( sse41_result != cpucaps.hasStreamingSIMD4Extensions )
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{
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Console::Notice( "SSE4 Detection Inconsistency: cpuid=%s, test_result=%s",
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params bool_to_char( cpucaps.hasStreamingSIMD4Extensions ), bool_to_char( sse41_result ) );
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cpucaps.hasStreamingSIMD4Extensions = sse41_result;
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}
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}
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else { Console::Error("Error: Failed to allocate memory for SSE3 State detection."); }
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else
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Console::Notice(
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"Notice: Could not allocate memory for SSE3/4 detection.\n"
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"\tRelying on CPUID results. [this is not an error]"
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);
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#endif
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//////////////////////////////////////
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// Core Counting!
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@ -54,12 +54,14 @@ struct CAPABILITIES
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u32 hasStreamingSIMD3Extensions;
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u32 hasSupplementalStreamingSIMD3Extensions;
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u32 hasStreamingSIMD4Extensions;
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u32 hasStreamingSIMD4Extensions2;
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// AMD-specific CPU Features
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u32 hasMultimediaExtensionsExt;
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u32 hasAMD64BitArchitecture;
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u32 has3DNOWInstructionExtensionsExt;
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u32 has3DNOWInstructionExtensions;
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u32 hasStreamingSIMD4ExtensionsA;
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};
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extern CAPABILITIES cpucaps;
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@ -73,6 +75,7 @@ struct CPUINFO
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u32 x86Flags; // Feature Flags
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u32 x86Flags2; // More Feature Flags
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u32 x86EFlags; // Extended Feature Flags
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u32 x86EFlags2; // Extended Feature Flags pg2
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u32 PhysicalCores;
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u32 LogicalCores;
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