mirror of https://github.com/PCSX2/pcsx2.git
--BTS r/m+r added for emitter
--Uses BTS + bit arrays for manual block tracking, instead of full invalidation.It makes some games much much faster and doesn't seem to affect he rest (still, testing is needed).Okami that uses some sort of SMC works .. but i'm sure there are some bugs left in it git-svn-id: http://pcsx2.googlecode.com/svn/branches/vtlb-exp@951 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -1348,6 +1348,10 @@ void __fastcall dyna_block_discard(u32 start,u32 sz)
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Cpu->Clear(start,sz);
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}
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#define VTLB_ALLOC_SIZE (0x2900000) //this is a bit more than required
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extern u8* vtlb_alloc_base; //base of the memory array
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extern u8 vtlb_alloc_bits[VTLB_ALLOC_SIZE/16/8]; //328 kb
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void recRecompile( const u32 startpc )
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{
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u32 i = 0;
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@ -1708,6 +1712,56 @@ StartRecomp:
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MOV32ItoR(ECX, startpc);
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MOV32ItoR(EDX, sz);
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u32 mask=0;
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u32 writen=0;
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u32 writen_start=0;
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u32 lpc=inpage_ptr;
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u32 stg=pgsz;
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while(stg>0)
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{
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u32 bit=(lpc>>4)&7;
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if (mask==0)
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{
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//writen=bit;
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writen_start=(((u8*)PSM(lpc)-vtlb_alloc_base)>>4)/8;
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}
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mask|=1<<bit;
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if (bit==31)
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{
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vtlb_alloc_bits[writen_start]&=~mask;
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TEST32ItoM((uptr)&vtlb_alloc_bits[writen_start],mask);
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JNZ32(((u32)&dyna_block_discard)- ( (u32)x86Ptr[0] + 6 ));
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SysPrintf("%08X %d %d\n",mask,pgsz,pgsz>>4);
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mask=0;
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}
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//writen++;
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if (stg<=16)
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{
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lpc+=stg;
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stg=0;
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}
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else
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{
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lpc+=16;
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stg-=16;
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}
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}
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if (mask)
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{
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vtlb_alloc_bits[writen_start]&=~mask;
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TEST32ItoM((uptr)&vtlb_alloc_bits[writen_start],mask);
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JNZ32(((u32)&dyna_block_discard)- ( (u32)x86Ptr[0] + 6 ));
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SysPrintf("%08X %d %d\n",mask,pgsz,pgsz>>4);
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mask=0;
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}
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/*
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u32 lpc=inpage_ptr;
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u32 stg=pgsz;
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while(stg>0)
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@ -1719,6 +1773,7 @@ StartRecomp:
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stg-=4;
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lpc+=4;
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}
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*/
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DbgCon::WriteLn("Manual block @ %08X : %08X %d %d %d %d", params
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startpc,inpage_ptr,pgsz,0x1000-inpage_offs,inpage_sz,sz*4);
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}
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@ -28,6 +28,10 @@ u8* code_pos=0;
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u8* code_start=0;
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u32 code_sz;
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#define VTLB_ALLOC_SIZE (0x2900000) //this is a bit more than required
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extern u8* vtlb_alloc_base; //base of the memory array
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extern u8 vtlb_alloc_bits[VTLB_ALLOC_SIZE/16/8]; //328 kb
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union _vtlb_MemOpInfo
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{
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struct
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@ -82,6 +86,7 @@ void execuCode(bool set)
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u8* IndirectPlaceholderA()
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{
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//Add32 <eax>,imm, 6 bytes form.
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write8<_EmitterId_>( 0x81 );
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ModRM<_EmitterId_>( 3, 0, EAX );
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@ -100,7 +105,7 @@ void IndirectPlaceholderB(u8* pl,bool read,u32 sz,bool sx)
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u8* old=x86SetPtr(pl);
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inf.skip=old-pl-4;
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//Add32 <eax>,imm, 6 bytes form.
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//Add32 <eax>,imm, 6 bytes form, patch the imm value
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write32<_EmitterId_>( inf.full );
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x86SetPtr(old);
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}
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@ -470,7 +475,13 @@ static void _vtlb_DynGen_DirectWrite( u32 bits )
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break;
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}
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// SHR32ItoR(ECX,4);// do /16
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SHR32ItoR(ECX,4);// do /16
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uptr alloc_base=(uptr)vtlb_alloc_base;
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uptr bits_base=(uptr)vtlb_alloc_bits;
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bits_base-=(alloc_base>>4)/8;//in bytes
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BTS32MtoR(bits_base,ECX);
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// BTS_wtf(asdasd,ECX);
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}
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@ -2311,6 +2311,15 @@ emitterT void eAND32ItoM( uptr to, u32 from )
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}
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}
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/* bts imm32 to r32 */
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emitterT void eBTS32MtoR( uptr to, x86IntRegType from )
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{
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RexR(0,from);
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write8<I>( 0xf );
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write8<I>( 0xab );
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ModRM<I>( 0, from, DISP32 );
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write32<I>( MEMADDR(to, 4) );
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}
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/* and sign ext imm8 to m32 */
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emitterT void eAND32I8toM( uptr to, u8 from )
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@ -286,6 +286,7 @@
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#define AND8RtoM eAND8RtoM<_EmitterId_>
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#define AND8MtoR eAND8MtoR<_EmitterId_>
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#define AND8RtoR eAND8RtoR<_EmitterId_>
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#define BTS32MtoR eBTS32MtoR<_EmitterId_>
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#define NOT64R eNOT64R<_EmitterId_>
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#define NOT32R eNOT32R<_EmitterId_>
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#define NOT32M eNOT32M<_EmitterId_>
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