mirror of https://github.com/PCSX2/pcsx2.git
Clang: Format FiFo.cpp
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85d35311d0
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@ -41,16 +41,19 @@
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void __fastcall ReadFIFO_VIF1(mem128_t* out)
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{
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
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DevCon.Warning( "Reading from vif1 fifo when stalled" );
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
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DevCon.Warning("Reading from vif1 fifo when stalled");
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ZeroQWC(out); // Clear first in case no data gets written...
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pxAssertRel(vif1Regs.stat.FQC != 0, "FQC = 0 on VIF FIFO READ!");
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if (vif1Regs.stat.FDR) {
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if (vif1Regs.stat.FQC > vif1.GSLastDownloadSize) {
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if (vif1Regs.stat.FDR)
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{
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if (vif1Regs.stat.FQC > vif1.GSLastDownloadSize)
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{
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DevCon.Warning("Warning! GS Download size < FIFO count!");
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}
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if (vif1Regs.stat.FQC > 0) {
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if (vif1Regs.stat.FQC > 0)
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{
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GetMTGS().WaitGS();
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GetMTGS().SendPointerPacket(GS_RINGTYPE_INIT_READ_FIFO1, 0, out);
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GetMTGS().WaitGS(false); // wait without reg sync
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@ -69,68 +72,79 @@ void __fastcall ReadFIFO_VIF1(mem128_t* out)
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//////////////////////////////////////////////////////////////////////////
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// WriteFIFO Pages
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//
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void __fastcall WriteFIFO_VIF0(const mem128_t *value)
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void __fastcall WriteFIFO_VIF0(const mem128_t* value)
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{
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VIF_LOG("WriteFIFO/VIF0 <- %ls", WX_STR(value->ToString()));
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vif0ch.qwc += 1;
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if(vif0.irqoffset.value != 0 && vif0.vifstalled.enabled) DevCon.Warning("Offset on VIF0 FIFO start!");
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if (vif0.irqoffset.value != 0 && vif0.vifstalled.enabled)
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DevCon.Warning("Offset on VIF0 FIFO start!");
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bool ret = VIF0transfer((u32*)value, 4);
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if (vif0.cmd)
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{
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if(vif0.done && vif0ch.qwc == 0) vif0Regs.stat.VPS = VPS_WAITING;
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if (vif0.done && vif0ch.qwc == 0)
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vif0Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif0Regs.stat.VPS = VPS_IDLE;
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}
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pxAssertDev( ret, "vif stall code not implemented" );
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pxAssertDev(ret, "vif stall code not implemented");
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}
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void __fastcall WriteFIFO_VIF1(const mem128_t *value)
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void __fastcall WriteFIFO_VIF1(const mem128_t* value)
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{
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VIF_LOG("WriteFIFO/VIF1 <- %ls", WX_STR(value->ToString()));
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if (vif1Regs.stat.FDR) {
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if (vif1Regs.stat.FDR)
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{
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DevCon.Warning("writing to fifo when fdr is set!");
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}
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) ) {
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
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{
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DevCon.Warning("writing to vif1 fifo when stalled");
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}
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if (vif1.irqoffset.value != 0 && vif1.vifstalled.enabled) {
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if (vif1.irqoffset.value != 0 && vif1.vifstalled.enabled)
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{
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DevCon.Warning("Offset on VIF1 FIFO start!");
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}
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bool ret = VIF1transfer((u32*)value, 4);
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if (vif1.cmd) {
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if (vif1.done && !vif1ch.qwc) vif1Regs.stat.VPS = VPS_WAITING;
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if (vif1.cmd)
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{
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if (vif1.done && !vif1ch.qwc)
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vif1Regs.stat.VPS = VPS_WAITING;
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}
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else vif1Regs.stat.VPS = VPS_IDLE;
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else
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vif1Regs.stat.VPS = VPS_IDLE;
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if( gifRegs.stat.APATH == 2 && gifUnit.gifPath[1].isDone())
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if (gifRegs.stat.APATH == 2 && gifUnit.gifPath[1].isDone())
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{
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gifRegs.stat.APATH = 0;
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gifRegs.stat.OPH = 0;
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vif1Regs.stat.VGW = false; //Let vif continue if it's stuck on a flush
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if(gifUnit.checkPaths(1,0,1)) gifUnit.Execute(false, true);
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if (gifUnit.checkPaths(1, 0, 1))
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gifUnit.Execute(false, true);
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}
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pxAssertDev( ret, "vif stall code not implemented" );
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pxAssertDev(ret, "vif stall code not implemented");
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}
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void __fastcall WriteFIFO_GIF(const mem128_t *value)
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void __fastcall WriteFIFO_GIF(const mem128_t* value)
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{
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GUNIT_LOG("WriteFIFO_GIF()");
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if ((!gifUnit.CanDoPath3() || gif_fifo.fifoSize > 0)) {
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if ((!gifUnit.CanDoPath3() || gif_fifo.fifoSize > 0))
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{
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//DevCon.Warning("GIF FIFO HW Write");
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gif_fifo.write_fifo((u32*)value, 1);
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gif_fifo.read_fifo();
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}
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else {
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else
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{
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gifUnit.TransferGSPacketData(GIF_TRANS_FIFO, (u8*)value, 16);
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}
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@ -144,9 +158,8 @@ void __fastcall WriteFIFO_GIF(const mem128_t *value)
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if (gifUnit.gifPath[GIF_PATH_3].state == GIF_PATH_IDLE || gifUnit.gifPath[GIF_PATH_3].state == GIF_PATH_WAIT)
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{
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if (gifUnit.checkPaths(1, 1, 0)) gifUnit.Execute(false, true);
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if (gifUnit.checkPaths(1, 1, 0))
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gifUnit.Execute(false, true);
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}
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}
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}
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