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Apparently the sio didn't really like me setting count to 1 every byte. Hardcoded a block size of 0x24 for now, since it's what the bcr in the bios has. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2505 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz 2010-01-24 02:16:06 +00:00
parent 287bd773f8
commit 3eb3991b9a
3 changed files with 44 additions and 11 deletions
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4
pcsx2/IopDma.cpp
View File

@ -381,7 +381,7 @@ void IopDmaStart(int channel)
} }
} }
Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d dir=%d", channel, size, chcr&DMA_CTRL_DIRECTION); Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d(0x%08x), dir=%d", channel, size, bcr, chcr&DMA_CTRL_DIRECTION);
IopDmaHandlers[channel].REG_CHCR() |= DMA_CTRL_ACTIVE; IopDmaHandlers[channel].REG_CHCR() |= DMA_CTRL_ACTIVE;
IopDmaHandlers[channel].ByteCount = size; IopDmaHandlers[channel].ByteCount = size;
@ -452,7 +452,7 @@ void IopDmaUpdate(u32 elapsed)
ch->REG_MADR()+= ProcessedBytes; ch->REG_MADR()+= ProcessedBytes;
ch->ByteCount -= ProcessedBytes; ch->ByteCount -= ProcessedBytes;
NextUpdateDelay = ProcessedBytes/4; // / ch->Width; NextUpdateDelay = ProcessedBytes/2; // / ch->Width;
} }
if (RequestedDelay != 0) NextUpdateDelay = RequestedDelay; if (RequestedDelay != 0) NextUpdateDelay = RequestedDelay;

25
pcsx2/IopDma.h
View File

@ -25,7 +25,30 @@
typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
typedef void (* DmaIHandler)(s32 channel); typedef void (* DmaIHandler)(s32 channel);
class DmaHandlerInfo // unused for now
class DmaBcrReg
{
public:
union {
struct {
u32 size:16;
u32 count:16;
};
u32 whole;
};
DmaBcrReg(u32& value)
{
whole=value;
}
u32 Bytes()
{
return 4*size*count;
}
};
struct DmaHandlerInfo
{ {
public: public:
const char* Name; const char* Name;

26
pcsx2/IopSio2.cpp
View File

@ -239,7 +239,7 @@ s32 sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
} }
} }
//PSX_INT(IopEvt_Dma12,read/2); // Interrupts should always occur at the end PSX_INT(IopEvt_Dma12,read/4); // Interrupts should always occur at the end
*bytesProcessed = read; *bytesProcessed = read;
#endif #endif
@ -261,19 +261,29 @@ s32 sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
int written = 0; int written = 0;
for(int i = 0; i < bytesLeft; i++) // FIXME: temp code, might need to implement properly
int bs = 0x24;
int bc = bytesLeft / (bs*4);
int ts = bc * bs * 4;
assert(ts == bytesLeft);
for(int j=0;j<bc;j++)
{ {
sio.count = 1; sio.count = 1;
sio2_fifoIn(*(data++)); for(int i=0;i<(bs*4);i++)
written++;
if((sio2.packet.sendSize == BUFSIZE))
{ {
//written = bytesLeft; sio2_fifoIn(*(data++));
break; written++;
if((sio2.packet.sendSize == BUFSIZE))
{
//written = bytesLeft;
break;
}
} }
} }
//PSX_INT(IopEvt_Dma11,written/2); // Interrupts should always occur at the end PSX_INT(IopEvt_Dma11,written/4); // Interrupts should always occur at the end
*bytesProcessed = written; *bytesProcessed = written;
#endif #endif