From 3eb3991b9ab93eefb87a0e243f2f041b7cec15c6 Mon Sep 17 00:00:00 2001
From: gigaherz <gigaherz@96395faa-99c1-11dd-bbfe-3dabce05a288>
Date: Sun, 24 Jan 2010 02:16:06 +0000
Subject: [PATCH] Apparently the sio didn't really like me setting count to 1
 every byte. Hardcoded a block size of 0x24 for now, since it's what the bcr
 in the bios has.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2505 96395faa-99c1-11dd-bbfe-3dabce05a288
---
 pcsx2/IopDma.cpp  |  4 ++--
 pcsx2/IopDma.h    | 25 ++++++++++++++++++++++++-
 pcsx2/IopSio2.cpp | 26 ++++++++++++++++++--------
 3 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/pcsx2/IopDma.cpp b/pcsx2/IopDma.cpp
index 5b91188c77..697c8feb96 100644
--- a/pcsx2/IopDma.cpp
+++ b/pcsx2/IopDma.cpp
@@ -381,7 +381,7 @@ void IopDmaStart(int channel)
 		}
 	}
 
-	Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d dir=%d", channel, size, chcr&DMA_CTRL_DIRECTION);
+	Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d(0x%08x), dir=%d", channel, size, bcr, chcr&DMA_CTRL_DIRECTION);
 
 	IopDmaHandlers[channel].REG_CHCR() |= DMA_CTRL_ACTIVE;
 	IopDmaHandlers[channel].ByteCount = size;
@@ -452,7 +452,7 @@ void IopDmaUpdate(u32 elapsed)
 							ch->REG_MADR()+= ProcessedBytes;
 							ch->ByteCount -= ProcessedBytes;
 
-							NextUpdateDelay = ProcessedBytes/4; // / ch->Width;
+							NextUpdateDelay = ProcessedBytes/2; // / ch->Width;
 						}
 
 						if (RequestedDelay != 0) NextUpdateDelay = RequestedDelay;
diff --git a/pcsx2/IopDma.h b/pcsx2/IopDma.h
index a7c1d4b6fc..df173b11bf 100644
--- a/pcsx2/IopDma.h
+++ b/pcsx2/IopDma.h
@@ -25,7 +25,30 @@
 typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
 typedef void (* DmaIHandler)(s32 channel);
 
-class DmaHandlerInfo
+// unused for now
+class DmaBcrReg
+{
+public:
+	union {
+		struct {
+			u32 size:16;
+			u32 count:16;
+		};
+		u32 whole;
+	};
+
+	DmaBcrReg(u32& value)
+	{
+		whole=value;
+	}
+
+	u32 Bytes()
+	{
+		return 4*size*count;
+	}
+};
+
+struct DmaHandlerInfo
 {
 public:
 	const char* Name;
diff --git a/pcsx2/IopSio2.cpp b/pcsx2/IopSio2.cpp
index c930543c07..04b9494f50 100644
--- a/pcsx2/IopSio2.cpp
+++ b/pcsx2/IopSio2.cpp
@@ -239,7 +239,7 @@ s32 sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
 		}
 	}
 
-	//PSX_INT(IopEvt_Dma12,read/2);	// Interrupts should always occur at the end
+	PSX_INT(IopEvt_Dma12,read/4);	// Interrupts should always occur at the end
 
 	*bytesProcessed = read;
 #endif
@@ -261,19 +261,29 @@ s32 sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
 
 	int written = 0;
 
-	for(int i = 0; i < bytesLeft; i++)
+	// FIXME: temp code, might need to implement properly
+	int bs = 0x24;
+	int bc = bytesLeft / (bs*4);
+	int ts = bc * bs * 4;
+
+	assert(ts == bytesLeft);
+
+	for(int j=0;j<bc;j++)
 	{
 		sio.count = 1;
-		sio2_fifoIn(*(data++));
-		written++;
-		if((sio2.packet.sendSize == BUFSIZE))
+		for(int i=0;i<(bs*4);i++)
 		{
-			//written = bytesLeft;
-			break;
+			sio2_fifoIn(*(data++));
+			written++;
+			if((sio2.packet.sendSize == BUFSIZE))
+			{
+				//written = bytesLeft;
+				break;
+			}
 		}
 	}
 
-	//PSX_INT(IopEvt_Dma11,written/2);	// Interrupts should always occur at the end
+	PSX_INT(IopEvt_Dma11,written/4);	// Interrupts should always occur at the end
 
 	*bytesProcessed = written;
 #endif