mirror of https://github.com/PCSX2/pcsx2.git
Sif: Revert one of the changes from r2490. Rework safeDmaGetAddr.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2509 96395faa-99c1-11dd-bbfe-3dabce05a288
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60987c08eb
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59
pcsx2/Dmac.h
59
pcsx2/Dmac.h
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@ -196,7 +196,8 @@ union tDMA_QWC {
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void reset() { _u32 = 0; }
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wxString desc() { return wxsFormat(L"QWC: 0x%x", _u32); }
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};
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static __forceinline void setDmacStat(u32 num);
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static __forceinline tDMA_TAG *dmaGetAddr(u32 addr);
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static __forceinline void throwBusError(const char *s);
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struct DMACh {
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@ -226,8 +227,6 @@ struct DMACh {
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bool transfer(const char *s, tDMA_TAG* ptag)
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{
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//chcrTransfer(ptag);
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if (ptag == NULL) // Is ptag empty?
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{
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throwBusError(s);
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@ -245,6 +244,35 @@ struct DMACh {
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qwcTransfer(ptag);
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}
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tDMA_TAG *getAddr(u32 addr, u32 num)
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{
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tDMA_TAG *ptr = dmaGetAddr(addr);
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if (ptr == NULL)
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{
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throwBusError("dmaGetAddr");
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setDmacStat(num);
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chcr.STR = false;
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}
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return ptr;
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}
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tDMA_TAG *DMAtransfer(u32 addr, u32 num)
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{
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tDMA_TAG *tag = getAddr(addr, num);
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if (tag == NULL) return NULL;
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chcrTransfer(tag);
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qwcTransfer(tag);
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return tag;
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}
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tDMA_TAG dma_tag()
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{
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return DMA_TAG(chcr._u32);
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}
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wxString cmq_to_str()
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{
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx", chcr._u32, madr, qwc);
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@ -543,7 +571,7 @@ struct INTCregisters
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u32 padding[3];
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tINTC_MASK mask;
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};
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#define dmacRegs ((DMACregisters*)(PS2MEM_HW+0xE000))
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#define intcRegs ((INTCregisters*)(PS2MEM_HW+0xF000))
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@ -553,6 +581,13 @@ static __forceinline void throwBusError(const char *s)
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dmacRegs->stat.BEIS = true;
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}
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static __forceinline void setDmacStat(u32 num)
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{
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dmacRegs->stat.set_flags(1 << num);
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}
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static __forceinline bool inScratchpad(u32 addr)
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{
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return ((addr >=0x70000000) && (addr <= 0x70003fff));
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@ -583,22 +618,6 @@ static __forceinline tDMA_TAG *dmaGetAddr(u32 addr)
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return ptr;
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}
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static __forceinline tDMA_TAG *safeDmaGetAddr(DMACh *dma, u32 addr, u32 num)
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{
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tDMA_TAG *ptr = dmaGetAddr(addr);
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if (ptr == NULL)
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{
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// DMA Error
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dmacRegs->stat.BEIS = true; // BUS Error
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// DMA End
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dmacRegs->stat.set_flags(1 << num);
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dma->chcr.STR = false;
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}
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return ptr;
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}
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void hwIntcIrq(int n);
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void hwDmacIrq(int n);
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@ -44,8 +44,12 @@ static __forceinline bool SifEERead(int &cycles)
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
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SIF_LOG("----------- %lX of %lX", readSize << 2, sif0dma->qwc << 2);
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ptag = safeDmaGetAddr(sif0dma, sif0dma->madr, DMAC_SIF0);
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if (ptag == NULL) return false;
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ptag = sif0dma->getAddr(sif0dma->madr, DMAC_SIF0);
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if (ptag == NULL)
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{
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DevCon.Warning("SIFEERead: ptag == NULL");
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return false;
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}
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sif0.fifo.read((u32*)ptag, readSize << 2);
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@ -61,14 +65,19 @@ static __forceinline bool SifEERead(int &cycles)
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static __forceinline bool SifEEWrite(int &cycles)
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{
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// There's some data ready to transfer into the fifo..
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tDMA_TAG *pTag;
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tDMA_TAG *ptag;
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const int writeSize = min((s32)sif1dma->qwc, (FIFO_SIF_W - sif1.fifo.size) / 4);
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if (writeSize == 0) { /*Console.Warning("SifEEWrite writeSize is 0"); return false;*/ }
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pTag = safeDmaGetAddr(sif1dma, sif1dma->madr, DMAC_SIF1);
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if (pTag == NULL) return false;
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ptag = sif1dma->getAddr(sif1dma->madr, DMAC_SIF1);
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if (ptag == NULL)
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{
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DevCon.Warning("SIFEEWrite: ptag == NULL");
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return false;
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}
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sif1.fifo.write((u32*)pTag, writeSize << 2);
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sif1.fifo.write((u32*)ptag, writeSize << 2);
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sif1dma->madr += writeSize << 4;
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cycles += writeSize; // fixme : BIAS is factored in above
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@ -230,10 +239,12 @@ static __forceinline void SIF1EEDma(int &cycles, bool &done)
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// Process DMA tag at sif1dma->tadr
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done = false;
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ptag = safeDmaGetAddr(sif1dma, sif1dma->tadr, DMAC_SIF1);
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if (ptag == NULL) return;
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sif1dma->unsafeTransfer(ptag);
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ptag = sif1dma->DMAtransfer(sif1dma->tadr, DMAC_SIF1);
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if (ptag == NULL)
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{
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DevCon.Warning("SIF1EEDma: ptag == NULL");
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return;
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}
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if (sif1dma->chcr.TTE)
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{
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@ -355,6 +366,11 @@ static __forceinline void SIF0IOPDma(int &psxCycles, bool &done)
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static __forceinline void SIF1IOPDma(int &psxCycles, bool &done)
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{
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if (sif1.counter > 0)
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{
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SifIOPRead(psxCycles);
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}
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if (sif1.counter <= 0)
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{
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tDMA_TAG sTag(sif1.data.data);
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@ -394,11 +410,6 @@ static __forceinline void SIF1IOPDma(int &psxCycles, bool &done)
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done = false;
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}
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}
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if (sif1.counter > 0)
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{
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SifIOPRead(psxCycles);
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}
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}
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// Tests if iop & ee are busy before the while statement,
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