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Merge pull request #452 from turtleli/fix-linux-build-avx2-with-tsx-disabled 

GSdx: Linux: Fix build failure on AVX2 processor with disabled TSX, enable SSE4.2, SSE4.1, SSSE3 builds
This commit is contained in:
Gregory Hainaut 2015-03-01 17:53:21 +01:00
parent c1604c4b38 1222bcbf6e
commit 3b5367c5b7
3 changed files with 20 additions and 5 deletions
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2
plugins/GSdx/GSRendererSW.cpp
View File

@ -1519,7 +1519,7 @@ GSRendererSW::SharedData::~SharedData()
fflush(s_fp);}
}
static TransactionScope::Lock s_lock;
//static TransactionScope::Lock s_lock;
void GSRendererSW::SharedData::UsePages(const uint32* fb_pages, int fpsm, const uint32* zb_pages, int zpsm)
{

13
plugins/GSdx/GSThread.h
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@ -386,7 +386,7 @@ public:
};
// http://software.intel.com/en-us/blogs/2012/11/06/exploring-intel-transactional-synchronization-extensions-with-intel-software
#if 0
class TransactionScope
{
public:
@ -428,7 +428,12 @@ public:
TransactionScope(Lock& fallBackLock_, int max_retries = 3)
: fallBackLock(fallBackLock_)
{
#if _M_SSE >= 0x501
// The TSX (RTM/HLE) instructions on Intel AVX2 CPUs may either be
// absent or disabled (see errata HSD136 and specification change at
// http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf)
// This can cause builds for AVX2 CPUs to fail with GCC/Clang on Linux,
// so check that the RTM instructions are actually available.
#if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__)
int nretries = 0;
@ -471,7 +476,7 @@ public:
{
fallBackLock.unlock();
}
#if _M_SSE >= 0x501
#if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__)
else
{
_xend();
@ -479,4 +484,4 @@ public:
#endif
}
};
#endif

10
plugins/GSdx/stdafx.h
View File

@ -279,6 +279,16 @@ struct aligned_free_second {template<class T> void operator()(T& p) {_aligned_fr
#define _M_SSE 0x501
#elif defined(__AVX__)
#define _M_SSE 0x500
#elif defined(__SSE4_2__)
#define _M_SSE 0x402
#elif defined(__SSE4_1__)
#define _M_SSE 0x401
#elif defined(__SSSE3__)
#define _M_SSE 0x301
#elif defined(__SSE2__)
#define _M_SSE 0x200
#elif defined(__SSE__)
#define _M_SSE 0x100
#endif
#endif