From 9b572d2d47178881708a1bed423ff38c9a7c9007 Mon Sep 17 00:00:00 2001 From: turtleli Date: Thu, 12 Feb 2015 14:31:12 +0000 Subject: [PATCH 1/4] GSdx: Linux: Fix AVX2 CPU build with TSX disabled On Linux, CPUs with AVX2 instruction sets that have TSX disabled (by microcode update or otherwise) fail to build GSdx. The __RTM__ macro is undefined, with leads to the TSX RTM instruction set (_xbegin, _xend, _xabort, etc.) being unavailable. Modify the preprocessor check so that the RTM instructions are only used if available. --- plugins/GSdx/GSThread.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plugins/GSdx/GSThread.h b/plugins/GSdx/GSThread.h index a773e5251b..45d5daca69 100644 --- a/plugins/GSdx/GSThread.h +++ b/plugins/GSdx/GSThread.h @@ -485,7 +485,7 @@ public: TransactionScope(Lock& fallBackLock_, int max_retries = 3) : fallBackLock(fallBackLock_) { - #if _M_SSE >= 0x501 + #if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__) int nretries = 0; @@ -528,7 +528,7 @@ public: { fallBackLock.unlock(); } - #if _M_SSE >= 0x501 + #if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__) else { _xend(); From 329953ebc3e4bb45c31a085f38b63e53ad99ba84 Mon Sep 17 00:00:00 2001 From: Jonathan Li Date: Thu, 12 Feb 2015 17:49:31 +0000 Subject: [PATCH 2/4] GSdx: Linux: Enable SSE4.2, SSE4.1 and SSE3 builds --- plugins/GSdx/stdafx.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/plugins/GSdx/stdafx.h b/plugins/GSdx/stdafx.h index 16c80c9480..cda44482f1 100644 --- a/plugins/GSdx/stdafx.h +++ b/plugins/GSdx/stdafx.h @@ -279,6 +279,16 @@ struct aligned_free_second {template void operator()(T& p) {_aligned_fr #define _M_SSE 0x501 #elif defined(__AVX__) #define _M_SSE 0x500 +#elif defined(__SSE4_2__) + #define _M_SSE 0x402 +#elif defined(__SSE4_1__) + #define _M_SSE 0x401 +#elif defined(__SSSE3__) + #define _M_SSE 0x301 +#elif defined(__SSE2__) + #define _M_SSE 0x200 +#elif defined(__SSE__) + #define _M_SSE 0x100 #endif #endif From 13c0e6f5ef9f6cbdd3b0bf663fde72bcffdbba6c Mon Sep 17 00:00:00 2001 From: Jonathan Li Date: Sat, 28 Feb 2015 13:20:01 +0000 Subject: [PATCH 3/4] GSdx: Explain TransactionScope changes --- plugins/GSdx/GSThread.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/plugins/GSdx/GSThread.h b/plugins/GSdx/GSThread.h index 45d5daca69..3738790f8b 100644 --- a/plugins/GSdx/GSThread.h +++ b/plugins/GSdx/GSThread.h @@ -485,6 +485,11 @@ public: TransactionScope(Lock& fallBackLock_, int max_retries = 3) : fallBackLock(fallBackLock_) { + // The TSX (RTM/HLE) instructions on Intel AVX2 CPUs may either be + // absent or disabled (see errata HSD136 and specification change at + // http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf) + // This can cause builds for AVX2 CPUs to fail with GCC/Clang on Linux, + // so check that the RTM instructions are actually available. #if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__) int nretries = 0; From 1222bcbf6e0fe088ca197bddb4b355d12e9abf00 Mon Sep 17 00:00:00 2001 From: Jonathan Li Date: Sun, 1 Mar 2015 16:40:48 +0000 Subject: [PATCH 4/4] GSdx: Comment out TransactionScope code The TransactionScope class is compiled but never used. Comment it out for now. --- plugins/GSdx/GSRendererSW.cpp | 2 +- plugins/GSdx/GSThread.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/plugins/GSdx/GSRendererSW.cpp b/plugins/GSdx/GSRendererSW.cpp index dff587fb8d..83fd2402f3 100644 --- a/plugins/GSdx/GSRendererSW.cpp +++ b/plugins/GSdx/GSRendererSW.cpp @@ -1519,7 +1519,7 @@ GSRendererSW::SharedData::~SharedData() fflush(s_fp);} } -static TransactionScope::Lock s_lock; +//static TransactionScope::Lock s_lock; void GSRendererSW::SharedData::UsePages(const uint32* fb_pages, int fpsm, const uint32* zb_pages, int zpsm) { diff --git a/plugins/GSdx/GSThread.h b/plugins/GSdx/GSThread.h index 3738790f8b..7b204db5b3 100644 --- a/plugins/GSdx/GSThread.h +++ b/plugins/GSdx/GSThread.h @@ -443,7 +443,7 @@ public: }; // http://software.intel.com/en-us/blogs/2012/11/06/exploring-intel-transactional-synchronization-extensions-with-intel-software - +#if 0 class TransactionScope { public: @@ -541,4 +541,4 @@ public: #endif } }; - +#endif