mirror of https://github.com/PCSX2/pcsx2.git
Merge branch 'uptr-addr'
This commit is contained in:
commit
38c548854e
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@ -696,6 +696,7 @@ template< typename T > void xWrite( T val );
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bool IsByteSizeDisp() const { return is_s8( Displacement ); }
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bool IsMem() const { return true; }
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bool IsReg() const { return false; }
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bool IsExtended() const { return false; } // Non sense but ease template
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operator xAddressVoid()
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{
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@ -168,11 +168,18 @@ void SysMtgsThread::PostVsyncStart()
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m_sem_Vsync.WaitNoCancel();
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}
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struct PacketTagType
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union PacketTagType
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{
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struct {
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u32 command;
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u32 data[3];
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};
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struct {
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u32 _command;
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u32 _data[1];
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uptr pointer;
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};
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};
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static void dummyIrqCallback()
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{
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@ -456,7 +463,7 @@ void SysMtgsThread::ExecuteTaskInThread()
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case GS_RINGTYPE_FREEZE:
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{
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MTGS_FreezeData* data = (MTGS_FreezeData*)(*(uptr*)&tag.data[1]);
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MTGS_FreezeData* data = (MTGS_FreezeData*)tag.pointer;
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int mode = tag.data[0];
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data->retval = GetCorePlugins().DoFreeze( PluginId_GS, mode, data->fdata );
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}
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@ -486,13 +493,13 @@ void SysMtgsThread::ExecuteTaskInThread()
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case GS_RINGTYPE_INIT_READ_FIFO1:
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MTGS_LOG( "(MTGS Packet Read) ringtype=Fifo1" );
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if (GSinitReadFIFO)
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GSinitReadFIFO( (u64*)tag.data[1]);
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GSinitReadFIFO( (u64*)tag.pointer);
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break;
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case GS_RINGTYPE_INIT_READ_FIFO2:
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MTGS_LOG( "(MTGS Packet Read) ringtype=Fifo2, size=%d", tag.data[0] );
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if (GSinitReadFIFO2)
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GSinitReadFIFO2( (u64*)tag.data[1], tag.data[0]);
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GSinitReadFIFO2( (u64*)tag.pointer, tag.data[0]);
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break;
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#ifdef PCSX2_DEVBUILD
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@ -823,7 +830,7 @@ void SysMtgsThread::SendPointerPacket( MTGS_RingCommand type, u32 data0, void* d
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tag.command = type;
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tag.data[0] = data0;
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*(uptr*)&tag.data[1] = (uptr)data1;
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tag.pointer = (uptr)data1;
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_FinishSimplePacket();
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}
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@ -242,4 +242,8 @@ static void recLUT_SetPage(uptr reclut[0x10000], uptr hwlut[0x10000],
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hwlut[page] = 0u - (pagebase << 16);
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}
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#ifdef __x86_64__
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static_assert( sizeof(BASEBLOCK) == 8, "BASEBLOCK is not 8 bytes" );
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#else
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static_assert( sizeof(BASEBLOCK) == 4, "BASEBLOCK is not 4 bytes" );
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#endif
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@ -963,7 +963,7 @@ void _freeXMMregs()
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}
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}
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int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy)
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int _signExtendXMMtoM(uptr to, x86SSERegType from, int candestroy)
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{
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int t0reg;
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g_xmmtypes[from] = XMMT_INT;
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@ -186,12 +186,12 @@ u8 _hasFreeXMMreg();
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void _freeXMMregs();
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int _getNumXMMwrite();
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void _signExtendSFtoM(u32 mem);
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void _signExtendSFtoM(uptr mem);
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// returns new index of reg, lower 32 bits already in mmx
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// shift is used when the data is in the top bits of the mmx reg to begin with
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// a negative shift is for sign extension
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int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy); // returns true if reg destroyed
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int _signExtendXMMtoM(uptr to, x86SSERegType from, int candestroy); // returns true if reg destroyed
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//////////////////////
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// Instruction Info //
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@ -311,7 +311,7 @@ u8 _hasFreeMMXreg();
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void _freeMMXregs();
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int _getNumMMXwrite();
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int _signExtendMtoMMX(x86MMXRegType to, u32 mem);
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int _signExtendMtoMMX(x86MMXRegType to, uptr mem);
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int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32 gprfromreg);
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int _allocCheckGPRtoMMX(EEINST* pinst, int reg, int mode);
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@ -398,7 +398,8 @@ void _psxMoveGPRtoR(const xRegister32& to, int fromgpr)
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}
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}
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void _psxMoveGPRtoM(u32 to, int fromgpr)
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#if 0
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void _psxMoveGPRtoM(uptr to, int fromgpr)
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{
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if( PSX_IS_CONST1(fromgpr) )
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xMOV(ptr32[(u32*)(to)], g_psxConstRegs[fromgpr] );
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@ -408,7 +409,9 @@ void _psxMoveGPRtoM(u32 to, int fromgpr)
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xMOV(ptr[(void*)(to)], eax);
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}
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}
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#endif
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#if 0
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void _psxMoveGPRtoRm(x86IntRegType to, int fromgpr)
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{
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if( PSX_IS_CONST1(fromgpr) )
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@ -419,6 +422,7 @@ void _psxMoveGPRtoRm(x86IntRegType to, int fromgpr)
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xMOV(ptr[xAddressReg(to)], eax);
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}
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}
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#endif
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void _psxFlushCall(int flushtype)
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{
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@ -49,8 +49,10 @@ void _psxFlushCall(int flushtype);
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void _psxOnWriteReg(int reg);
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void _psxMoveGPRtoR(const x86Emitter::xRegister32& to, int fromgpr);
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void _psxMoveGPRtoM(u32 to, int fromgpr);
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#if 0
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void _psxMoveGPRtoM(uptr to, int fromgpr);
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void _psxMoveGPRtoRm(x86IntRegType to, int fromgpr);
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#endif
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extern u32 psxpc; // recompiler pc
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extern int psxbranch; // set for branch
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@ -105,7 +105,7 @@ u32* _eeGetConstReg(int reg);
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// finds where the GPR is stored and moves lower 32 bits to EAX
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void _eeMoveGPRtoR(const x86Emitter::xRegister32& to, int fromgpr);
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void _eeMoveGPRtoM(u32 to, int fromgpr);
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void _eeMoveGPRtoM(uptr to, int fromgpr);
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void _eeMoveGPRtoRm(x86IntRegType to, int fromgpr);
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void eeSignExtendTo(int gpr, bool onlyupper=false);
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@ -872,7 +872,7 @@ void SetFPUstate() {
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}
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}
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void _signExtendSFtoM(u32 mem)
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void _signExtendSFtoM(uptr mem)
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{
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xLAHF();
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xSAR(ax, 15);
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@ -880,7 +880,7 @@ void _signExtendSFtoM(u32 mem)
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xMOV(ptr[(void*)(mem)], eax);
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}
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int _signExtendMtoMMX(x86MMXRegType to, u32 mem)
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int _signExtendMtoMMX(x86MMXRegType to, uptr mem)
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{
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int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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@ -176,7 +176,7 @@ void _eeMoveGPRtoR(const xRegister32& to, int fromgpr)
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}
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}
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void _eeMoveGPRtoM(u32 to, int fromgpr)
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void _eeMoveGPRtoM(uptr to, int fromgpr)
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{
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if( GPR_IS_CONST1(fromgpr) )
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xMOV(ptr32[(u32*)(to)], g_cpuConstRegs[fromgpr].UL[0] );
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@ -36,7 +36,7 @@ extern uint64 g_real_texture_upload_byte;
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namespace PboPool {
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GLuint m_pool[PBO_POOL_SIZE];
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uint32 m_offset[PBO_POOL_SIZE];
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uptr m_offset[PBO_POOL_SIZE];
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char* m_map[PBO_POOL_SIZE];
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uint32 m_current_pbo = 0;
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uint32 m_size;
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@ -132,7 +132,7 @@ namespace PboPool {
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}
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}
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uint32 Offset() {
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uptr Offset() {
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return m_offset[m_current_pbo];
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}
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@ -31,7 +31,7 @@ namespace PboPool {
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char* Map(uint32 size);
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void Unmap();
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uint32 Offset();
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uptr Offset();
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void EndTransfer();
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void Init();
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@ -120,10 +120,6 @@ using namespace std;
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using namespace stdext;
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#endif
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#ifdef __linux__
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#include <sys/stat.h> // mkdir
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#endif
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#ifdef _WINDOWS
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// Note use GL/glcorearb.h on the future
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@ -195,6 +191,8 @@ using namespace stdext;
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#include <GL/glext.h>
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#include "GLLoader.h"
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#include <sys/stat.h> // mkdir
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#define DIRECTORY_SEPARATOR '/'
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#endif
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@ -206,6 +204,8 @@ using namespace stdext;
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#define EXPORT_C_(type) extern "C" __declspec(dllexport) type __stdcall
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#define EXPORT_C EXPORT_C_(void)
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#define ALIGN_STACK(n) __aligned(int, n) __dummy;
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#else
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#define __aligned(t, n) t __attribute__((aligned(n)))
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@ -221,8 +221,18 @@ using namespace stdext;
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// #define __forceinline __inline__ __attribute__((__always_inline__,__gnu_inline__))
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#define __assume(c) do { if (!(c)) __builtin_unreachable(); } while(0)
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// GCC removes the variable as dead code and generates some warnings.
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// Stack is automatically realigned due to SSE/AVX operations
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#define ALIGN_STACK(n) (void)0;
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#else
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// TODO Check clang behavior
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#define ALIGN_STACK(n) __aligned(int, n) __dummy;
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#endif
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#endif
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extern string format(const char* fmt, ...);
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@ -236,14 +246,6 @@ struct aligned_free_second {template<class T> void operator()(T& p) {_aligned_fr
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#define countof(a) (sizeof(a) / sizeof(a[0]))
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// GCC removes the variable as dead code and generates some warnings.
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// Stack is automatically realigned due to SSE/AVX operations
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#ifdef __GNUC__
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#define ALIGN_STACK(n) (void)0;
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#else
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#define ALIGN_STACK(n) __aligned(int, n) __dummy;
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#endif
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#ifndef RESTRICT
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#ifdef __INTEL_COMPILER
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@ -284,7 +286,7 @@ struct aligned_free_second {template<class T> void operator()(T& p) {_aligned_fr
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#endif
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// sse
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#ifdef __GNUC__
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#if defined(__GNUC__) && !defined(__x86_64__)
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// Convert gcc see define into GSdx (windows) define
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#if defined(__AVX2__)
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#define _M_SSE 0x501
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@ -301,6 +303,7 @@ struct aligned_free_second {template<class T> void operator()(T& p) {_aligned_fr
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#elif defined(__SSE__)
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#define _M_SSE 0x100
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#endif
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#endif
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#if !defined(_M_SSE) && (!defined(_WINDOWS) || defined(_M_AMD64) || defined(_M_IX86_FP) && _M_IX86_FP >= 2)
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