mirror of https://github.com/PCSX2/pcsx2.git
Apply recent Iop HwRegister handler changes to the EE's mapping [EE has direct access to IOP memory and registers through a special tlb mapping, intended for ps2dev debugging, and generally used by bios only during boot-up).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1133 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
db41e52940
commit
3647a635bc
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@ -1313,26 +1313,19 @@ void psxHwWrite32(u32 add, u32 value) {
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PSXHW_LOG("*Known 32bit write at address %lx value %lx", add, value);
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}
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u8 psxHw4Read8(u32 add)
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__forceinline u8 psxHw4Read8(u32 add)
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{
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//u8 hard;
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u16 mem = add & 0xFF;
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//Console::WriteLn("psxHw4Read8 0x%x, %x", params add, mem);
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return cdvdRead(mem);
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//PSXHW_LOG( "Known 8bit read from addr 0x%x = 0x%x", add, hard );
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//return hard;
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u8 ret = cdvdRead(mem);
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PSXHW_LOG("HwRead8 from Cdvd [segment 0x1f40], addr 0x%02x = 0x%02x", mem, ret);
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return ret;
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}
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void psxHw4Write8(u32 add, u8 value)
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__forceinline void psxHw4Write8(u32 add, u8 value)
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{
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u16 mem = add & 0xFF;
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//Console::WriteLn("psxHw4Write8 0x%x, %x", params add, mem);
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u8 mem = (u8)add; // only lower 8 bits are relevant (cdvd regs mirror across the page)
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cdvdWrite(mem, value);
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PSXHW_LOG("Known 8bit write to addr 0x%x = 0x%x", add, value);
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PSXHW_LOG("HwWrite8 to Cdvd [segment 0x1f40], addr 0x%02x = 0x%02x", mem, value);
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}
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void psxDmaInterrupt(int n)
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@ -220,28 +220,19 @@ extern void psxSetNextBranchDelta( s32 delta );
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extern int iopTestCycle( u32 startCycle, s32 delta );
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extern void _iopTestInterrupts();
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void psxHwReset();
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// Depreciated : Use iopHwRead* functions defined in IopMem.h instead.
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u8 psxHwRead8 (u32 add);
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u16 psxHwRead16(u32 add);
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u32 psxHwRead32(u32 add);
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// Depreciated : Use iopHwWrite* functions defined in IopMem.h instead.
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void psxHwWrite8 (u32 add, u8 value);
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void psxHwWrite16(u32 add, u16 value);
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void psxHwWrite32(u32 add, u32 value);
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u8 psxHw4Read8 (u32 add);
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void psxHw4Write8(u32 add, u8 value);
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extern void psxHwReset();
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extern u8 psxHw4Read8 (u32 add);
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extern void psxHw4Write8(u32 add, u8 value);
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void psxDmaInterrupt(int n);
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void psxDmaInterrupt2(int n);
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int psxHwFreeze(gzFile f, int Mode);
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int psxHwConstRead8(u32 x86reg, u32 add, u32 sign);
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int psxHwConstRead16(u32 x86reg, u32 add, u32 sign);
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int psxHwConstRead32(u32 x86reg, u32 add);
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void psxHwConstWrite8(u32 add, int mmreg);
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void psxHwConstWrite16(u32 add, int mmreg);
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void psxHwConstWrite32(u32 add, int mmreg);
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int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign);
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void psxHw4ConstWrite8(u32 add, int mmreg);
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extern void psxDmaInterrupt(int n);
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extern void psxDmaInterrupt2(int n);
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@ -106,6 +106,14 @@ namespace IopMemory
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extern void __fastcall SifWrite16( u32 iopaddr, u16 data );
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extern void __fastcall SifWrite32( u32 iopaddr, u32 data );
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extern u8 __fastcall iopHwRead8_generic( u32 addr );
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extern u16 __fastcall iopHwRead16_generic( u32 addr );
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extern u32 __fastcall iopHwRead32_generic( u32 addr );
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extern void __fastcall iopHwWrite8_generic( u32 addr, u8 val );
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extern void __fastcall iopHwWrite16_generic( u32 addr, u16 val );
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extern void __fastcall iopHwWrite32_generic( u32 addr, u32 val );
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extern u8 __fastcall iopHwRead8_Page1( u32 iopaddr );
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extern u8 __fastcall iopHwRead8_Page3( u32 iopaddr );
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extern u8 __fastcall iopHwRead8_Page8( u32 iopaddr );
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@ -155,6 +155,10 @@ vtlbHandler hw_by_page[0x10];
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vtlbHandler gs_page_0;
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vtlbHandler gs_page_1;
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vtlbHandler iopHw_by_page_01;
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vtlbHandler iopHw_by_page_03;
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vtlbHandler iopHw_by_page_08;
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// Used to remap the VUmicro memory according to the VU0/VU1 dynarec setting.
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// (the VU memory operations are different for recs vs. interpreters)
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@ -195,12 +199,6 @@ void memMapPhy()
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vtlb_MapHandler(tlb_fallback_2,0x1f800000,0x10000);
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vtlb_MapHandler(tlb_fallback_8,0x1f900000,0x10000);
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#ifdef PCSX2_DEVBUILD
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// Bind fallback handlers used for logging purposes only.
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// In release mode the Vtlb will map these addresses directly instead of using
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// the read/write handlers (which just issue logs and do normal memOps)
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#endif
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// map specific optimized page handlers for HW accesses
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vtlb_MapHandler(hw_by_page[0x0], 0x10000000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x1], 0x10001000, 0x01000);
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@ -216,6 +214,11 @@ void memMapPhy()
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vtlb_MapHandler(gs_page_0, 0x12000000, 0x01000);
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vtlb_MapHandler(gs_page_1, 0x12001000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x1], 0x1f801000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x3], 0x1f803000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x8], 0x1f808000, 0x01000);
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}
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//Why is this required ?
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@ -245,8 +248,6 @@ mem8_t __fastcall _ext_memRead8 (u32 mem)
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{
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case 1: // hwm
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return hwRead8(mem);
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case 2: // psh
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return psxHwRead8(mem);
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case 3: // psh4
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return psxHw4Read8(mem);
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case 6: // gsm
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@ -301,8 +302,6 @@ mem32_t __fastcall _ext_memRead32(u32 mem)
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{
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switch (p)
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{
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case 2: // psh
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return psxHwRead32(mem);
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case 6: // gsm
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return gsRead32(mem);
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case 7: // dev9
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@ -354,8 +353,6 @@ void __fastcall _ext_memWrite8 (u32 mem, u8 value)
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case 1: // hwm
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hwWrite8(mem, value);
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return;
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case 2: // psh
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psxHwWrite8(mem, value); return;
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case 3: // psh4
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psxHw4Write8(mem, value); return;
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case 6: // gsm
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@ -398,8 +395,6 @@ template<int p>
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void __fastcall _ext_memWrite32(u32 mem, u32 value)
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{
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switch (p) {
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case 2: // psh
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psxHwWrite32(mem, value); return;
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case 6: // gsm
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gsWrite32(mem, value); return;
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case 7: // dev9
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@ -660,14 +655,13 @@ void memReset()
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vtlb_Init();
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tlb_fallback_0=vtlb_RegisterHandlerTempl1(_ext_mem,0);
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tlb_fallback_2=vtlb_RegisterHandlerTempl1(_ext_mem,2);
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tlb_fallback_3=vtlb_RegisterHandlerTempl1(_ext_mem,3);
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tlb_fallback_4=vtlb_RegisterHandlerTempl1(_ext_mem,4);
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tlb_fallback_5=vtlb_RegisterHandlerTempl1(_ext_mem,5);
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//tlb_fallback_6=vtlb_RegisterHandlerTempl1(_ext_mem,6);
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tlb_fallback_7=vtlb_RegisterHandlerTempl1(_ext_mem,7);
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tlb_fallback_8=vtlb_RegisterHandlerTempl1(_ext_mem,8);
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tlb_fallback_0 = vtlb_RegisterHandlerTempl1(_ext_mem,0);
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tlb_fallback_3 = vtlb_RegisterHandlerTempl1(_ext_mem,3);
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tlb_fallback_4 = vtlb_RegisterHandlerTempl1(_ext_mem,4);
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tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5);
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//tlb_fallback_6 = vtlb_RegisterHandlerTempl1(_ext_mem,6);
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tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7);
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tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8);
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// Dynarec versions of VUs
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vu0_micro_mem[0] = vtlb_RegisterHandlerTempl2(vuMicro,0,true);
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@ -677,7 +671,36 @@ void memReset()
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vu0_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,0,false);
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vu1_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,1,false);
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////////////
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// IOP's "secret" Hardware Register mapping, accessible from the EE (and meant for use
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// by debugging or BIOS only). The IOP's hw regs are divided into three main pages in
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// the 0x1f80 segment, and then another oddball page for CDVD in the 0x1f40 segment.
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//
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using namespace IopMemory;
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tlb_fallback_2 = vtlb_RegisterHandler(
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iopHwRead8_generic, iopHwRead16_generic, iopHwRead32_generic, _ext_memRead64<2>, _ext_memRead128<2>,
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iopHwWrite8_generic, iopHwWrite16_generic, iopHwWrite32_generic, _ext_memWrite64<2>, _ext_memWrite128<2>
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);
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iopHw_by_page_01 = vtlb_RegisterHandler(
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iopHwRead8_Page1, iopHwRead16_Page1, iopHwRead32_Page1, _ext_memRead64<2>, _ext_memRead128<2>,
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iopHwWrite8_Page1, iopHwWrite16_Page1, iopHwWrite32_Page1, _ext_memWrite64<2>, _ext_memWrite128<2>
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);
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iopHw_by_page_03 = vtlb_RegisterHandler(
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iopHwRead8_Page3, iopHwRead16_Page3, iopHwRead32_Page3, _ext_memRead64<2>, _ext_memRead128<2>,
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iopHwWrite8_Page3, iopHwWrite16_Page3, iopHwWrite32_Page3, _ext_memWrite64<2>, _ext_memWrite128<2>
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);
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iopHw_by_page_08 = vtlb_RegisterHandler(
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iopHwRead8_Page8, iopHwRead16_Page8, iopHwRead32_Page8, _ext_memRead64<2>, _ext_memRead128<2>,
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iopHwWrite8_Page8, iopHwWrite16_Page8, iopHwWrite32_Page8, _ext_memWrite64<2>, _ext_memWrite128<2>
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);
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//////////////////////////////////////////////////////////////////////////////////////////
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// psHw Optimized Mappings
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// The HW Registers have been split into pages to improve optimization.
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// Anything not explicitly mapped into one of the hw_by_page handlers will be handled
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@ -9,13 +9,13 @@
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// disabled in release builds. :)
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#ifdef _MSC_VER
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#ifdef PCSX2_DEVBUILD
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# define _SECURE_SCL 1
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# define _SECURE_SCL_THROWS 1
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# pragma warning(disable:4244) // disable warning C4244: '=' : conversion from 'big' to 'small', possible loss of data
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#else
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# define _SECURE_SCL 0
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#endif
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# ifdef PCSX2_DEVBUILD
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# define _SECURE_SCL 1
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# define _SECURE_SCL_THROWS 1
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# else
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# define _SECURE_SCL 0
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# endif
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#endif
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#define NOMINMAX // Disables other libs inclusion of their own min/max macros (we use std instead)
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@ -23,6 +23,41 @@ namespace IopMemory {
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using namespace Internal;
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// Template-compatible version of the psxHu macro. Used for writing.
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#define psxHu(mem) (*(u32*)&psxH[(mem) & 0xffff])
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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template< typename T >
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static __forceinline void _generic_write( u32 addr, T val )
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{
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int bitsize = (sizeof(T) == 1) ? 8 : ( (sizeof(T) == 2) ? 16 : 32 );
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PSXHW_LOG( "HwWrite%d to %s, addr 0x%08x = 0x%08x\n", bitsize, _log_GetIopHwName<T>(addr), addr, val );
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psxHu(addr) = val;
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}
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void __fastcall iopHwWrite8_generic( u32 addr, u8 val ) { _generic_write<u8>( addr, val ); }
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void __fastcall iopHwWrite16_generic( u32 addr, u16 val ) { _generic_write<u16>( addr, val ); }
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void __fastcall iopHwWrite32_generic( u32 addr, u32 val ) { _generic_write<u32>( addr, val ); }
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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template< typename T >
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static __forceinline T _generic_read( u32 addr )
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{
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int bitsize = (sizeof(T) == 1) ? 8 : ( (sizeof(T) == 2) ? 16 : 32 );
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T ret = psxHu(addr);
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PSXHW_LOG( "HwRead%d from %s, addr 0x%08x = 0x%08x\n", bitsize, _log_GetIopHwName<T>(addr), addr, ret );
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return ret;
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}
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u8 __fastcall iopHwRead8_generic( u32 addr ) { return _generic_read<u8>( addr ); }
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u16 __fastcall iopHwRead16_generic( u32 addr ) { return _generic_read<u16>( addr ); }
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u32 __fastcall iopHwRead32_generic( u32 addr ) { return _generic_read<u32>( addr ); }
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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void __fastcall iopHwWrite8_Page1( u32 addr, u8 val )
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@ -116,9 +151,6 @@ void __fastcall iopHwWrite8_Page8( u32 addr, u8 val )
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}
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// Template-compatible version of the psxHu macro. Used for writing.
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#define psxHu(mem) (*(u32*)&psxH[(mem) & 0xffff])
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//////////////////////////////////////////////////////////////////////////////////////////
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// Templated handler for both 32 and 16 bit write operations, to Page 1 registers.
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//
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@ -508,7 +540,6 @@ void __fastcall iopHwWrite32_Page8( u32 addr, u32 val )
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else psxHu32(addr) = val;
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PSXHW_LOG( "HwWrite32 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u32>( addr ), addr, val );
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}
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}
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@ -201,4 +201,4 @@ static __forceinline const char* _log_GetIopHwName( u32 addr )
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}
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}
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} };
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} };
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