diff --git a/pcsx2/IopHw.cpp b/pcsx2/IopHw.cpp index 80c5108f9e..2b4635fb20 100644 --- a/pcsx2/IopHw.cpp +++ b/pcsx2/IopHw.cpp @@ -1313,26 +1313,19 @@ void psxHwWrite32(u32 add, u32 value) { PSXHW_LOG("*Known 32bit write at address %lx value %lx", add, value); } -u8 psxHw4Read8(u32 add) +__forceinline u8 psxHw4Read8(u32 add) { - //u8 hard; u16 mem = add & 0xFF; - - //Console::WriteLn("psxHw4Read8 0x%x, %x", params add, mem); - return cdvdRead(mem); - - //PSXHW_LOG( "Known 8bit read from addr 0x%x = 0x%x", add, hard ); - - //return hard; + u8 ret = cdvdRead(mem); + PSXHW_LOG("HwRead8 from Cdvd [segment 0x1f40], addr 0x%02x = 0x%02x", mem, ret); + return ret; } -void psxHw4Write8(u32 add, u8 value) +__forceinline void psxHw4Write8(u32 add, u8 value) { - - u16 mem = add & 0xFF; - //Console::WriteLn("psxHw4Write8 0x%x, %x", params add, mem); + u8 mem = (u8)add; // only lower 8 bits are relevant (cdvd regs mirror across the page) cdvdWrite(mem, value); - PSXHW_LOG("Known 8bit write to addr 0x%x = 0x%x", add, value); + PSXHW_LOG("HwWrite8 to Cdvd [segment 0x1f40], addr 0x%02x = 0x%02x", mem, value); } void psxDmaInterrupt(int n) diff --git a/pcsx2/IopHw.h b/pcsx2/IopHw.h index 4b31f5f2c0..898b2de489 100644 --- a/pcsx2/IopHw.h +++ b/pcsx2/IopHw.h @@ -220,28 +220,19 @@ extern void psxSetNextBranchDelta( s32 delta ); extern int iopTestCycle( u32 startCycle, s32 delta ); extern void _iopTestInterrupts(); -void psxHwReset(); +// Depreciated : Use iopHwRead* functions defined in IopMem.h instead. u8 psxHwRead8 (u32 add); u16 psxHwRead16(u32 add); u32 psxHwRead32(u32 add); +// Depreciated : Use iopHwWrite* functions defined in IopMem.h instead. void psxHwWrite8 (u32 add, u8 value); void psxHwWrite16(u32 add, u16 value); void psxHwWrite32(u32 add, u32 value); -u8 psxHw4Read8 (u32 add); -void psxHw4Write8(u32 add, u8 value); +extern void psxHwReset(); +extern u8 psxHw4Read8 (u32 add); +extern void psxHw4Write8(u32 add, u8 value); -void psxDmaInterrupt(int n); -void psxDmaInterrupt2(int n); - -int psxHwFreeze(gzFile f, int Mode); - -int psxHwConstRead8(u32 x86reg, u32 add, u32 sign); -int psxHwConstRead16(u32 x86reg, u32 add, u32 sign); -int psxHwConstRead32(u32 x86reg, u32 add); -void psxHwConstWrite8(u32 add, int mmreg); -void psxHwConstWrite16(u32 add, int mmreg); -void psxHwConstWrite32(u32 add, int mmreg); -int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign); -void psxHw4ConstWrite8(u32 add, int mmreg); +extern void psxDmaInterrupt(int n); +extern void psxDmaInterrupt2(int n); diff --git a/pcsx2/IopMem.h b/pcsx2/IopMem.h index dc62657c45..ad618c6b7f 100644 --- a/pcsx2/IopMem.h +++ b/pcsx2/IopMem.h @@ -106,6 +106,14 @@ namespace IopMemory extern void __fastcall SifWrite16( u32 iopaddr, u16 data ); extern void __fastcall SifWrite32( u32 iopaddr, u32 data ); + extern u8 __fastcall iopHwRead8_generic( u32 addr ); + extern u16 __fastcall iopHwRead16_generic( u32 addr ); + extern u32 __fastcall iopHwRead32_generic( u32 addr ); + extern void __fastcall iopHwWrite8_generic( u32 addr, u8 val ); + extern void __fastcall iopHwWrite16_generic( u32 addr, u16 val ); + extern void __fastcall iopHwWrite32_generic( u32 addr, u32 val ); + + extern u8 __fastcall iopHwRead8_Page1( u32 iopaddr ); extern u8 __fastcall iopHwRead8_Page3( u32 iopaddr ); extern u8 __fastcall iopHwRead8_Page8( u32 iopaddr ); diff --git a/pcsx2/Memory.cpp b/pcsx2/Memory.cpp index a5eb775e2a..b791ce559a 100644 --- a/pcsx2/Memory.cpp +++ b/pcsx2/Memory.cpp @@ -155,6 +155,10 @@ vtlbHandler hw_by_page[0x10]; vtlbHandler gs_page_0; vtlbHandler gs_page_1; +vtlbHandler iopHw_by_page_01; +vtlbHandler iopHw_by_page_03; +vtlbHandler iopHw_by_page_08; + // Used to remap the VUmicro memory according to the VU0/VU1 dynarec setting. // (the VU memory operations are different for recs vs. interpreters) @@ -195,12 +199,6 @@ void memMapPhy() vtlb_MapHandler(tlb_fallback_2,0x1f800000,0x10000); vtlb_MapHandler(tlb_fallback_8,0x1f900000,0x10000); -#ifdef PCSX2_DEVBUILD - // Bind fallback handlers used for logging purposes only. - // In release mode the Vtlb will map these addresses directly instead of using - // the read/write handlers (which just issue logs and do normal memOps) -#endif - // map specific optimized page handlers for HW accesses vtlb_MapHandler(hw_by_page[0x0], 0x10000000, 0x01000); vtlb_MapHandler(hw_by_page[0x1], 0x10001000, 0x01000); @@ -216,6 +214,11 @@ void memMapPhy() vtlb_MapHandler(gs_page_0, 0x12000000, 0x01000); vtlb_MapHandler(gs_page_1, 0x12001000, 0x01000); + + vtlb_MapHandler(hw_by_page[0x1], 0x1f801000, 0x01000); + vtlb_MapHandler(hw_by_page[0x3], 0x1f803000, 0x01000); + vtlb_MapHandler(hw_by_page[0x8], 0x1f808000, 0x01000); + } //Why is this required ? @@ -245,8 +248,6 @@ mem8_t __fastcall _ext_memRead8 (u32 mem) { case 1: // hwm return hwRead8(mem); - case 2: // psh - return psxHwRead8(mem); case 3: // psh4 return psxHw4Read8(mem); case 6: // gsm @@ -301,8 +302,6 @@ mem32_t __fastcall _ext_memRead32(u32 mem) { switch (p) { - case 2: // psh - return psxHwRead32(mem); case 6: // gsm return gsRead32(mem); case 7: // dev9 @@ -354,8 +353,6 @@ void __fastcall _ext_memWrite8 (u32 mem, u8 value) case 1: // hwm hwWrite8(mem, value); return; - case 2: // psh - psxHwWrite8(mem, value); return; case 3: // psh4 psxHw4Write8(mem, value); return; case 6: // gsm @@ -398,8 +395,6 @@ template void __fastcall _ext_memWrite32(u32 mem, u32 value) { switch (p) { - case 2: // psh - psxHwWrite32(mem, value); return; case 6: // gsm gsWrite32(mem, value); return; case 7: // dev9 @@ -660,14 +655,13 @@ void memReset() vtlb_Init(); - tlb_fallback_0=vtlb_RegisterHandlerTempl1(_ext_mem,0); - tlb_fallback_2=vtlb_RegisterHandlerTempl1(_ext_mem,2); - tlb_fallback_3=vtlb_RegisterHandlerTempl1(_ext_mem,3); - tlb_fallback_4=vtlb_RegisterHandlerTempl1(_ext_mem,4); - tlb_fallback_5=vtlb_RegisterHandlerTempl1(_ext_mem,5); - //tlb_fallback_6=vtlb_RegisterHandlerTempl1(_ext_mem,6); - tlb_fallback_7=vtlb_RegisterHandlerTempl1(_ext_mem,7); - tlb_fallback_8=vtlb_RegisterHandlerTempl1(_ext_mem,8); + tlb_fallback_0 = vtlb_RegisterHandlerTempl1(_ext_mem,0); + tlb_fallback_3 = vtlb_RegisterHandlerTempl1(_ext_mem,3); + tlb_fallback_4 = vtlb_RegisterHandlerTempl1(_ext_mem,4); + tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5); + //tlb_fallback_6 = vtlb_RegisterHandlerTempl1(_ext_mem,6); + tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7); + tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8); // Dynarec versions of VUs vu0_micro_mem[0] = vtlb_RegisterHandlerTempl2(vuMicro,0,true); @@ -677,7 +671,36 @@ void memReset() vu0_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,0,false); vu1_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,1,false); - ////////////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////////////////////////////////// + // IOP's "secret" Hardware Register mapping, accessible from the EE (and meant for use + // by debugging or BIOS only). The IOP's hw regs are divided into three main pages in + // the 0x1f80 segment, and then another oddball page for CDVD in the 0x1f40 segment. + // + + using namespace IopMemory; + + tlb_fallback_2 = vtlb_RegisterHandler( + iopHwRead8_generic, iopHwRead16_generic, iopHwRead32_generic, _ext_memRead64<2>, _ext_memRead128<2>, + iopHwWrite8_generic, iopHwWrite16_generic, iopHwWrite32_generic, _ext_memWrite64<2>, _ext_memWrite128<2> + ); + + iopHw_by_page_01 = vtlb_RegisterHandler( + iopHwRead8_Page1, iopHwRead16_Page1, iopHwRead32_Page1, _ext_memRead64<2>, _ext_memRead128<2>, + iopHwWrite8_Page1, iopHwWrite16_Page1, iopHwWrite32_Page1, _ext_memWrite64<2>, _ext_memWrite128<2> + ); + + iopHw_by_page_03 = vtlb_RegisterHandler( + iopHwRead8_Page3, iopHwRead16_Page3, iopHwRead32_Page3, _ext_memRead64<2>, _ext_memRead128<2>, + iopHwWrite8_Page3, iopHwWrite16_Page3, iopHwWrite32_Page3, _ext_memWrite64<2>, _ext_memWrite128<2> + ); + + iopHw_by_page_08 = vtlb_RegisterHandler( + iopHwRead8_Page8, iopHwRead16_Page8, iopHwRead32_Page8, _ext_memRead64<2>, _ext_memRead128<2>, + iopHwWrite8_Page8, iopHwWrite16_Page8, iopHwWrite32_Page8, _ext_memWrite64<2>, _ext_memWrite128<2> + ); + + + ////////////////////////////////////////////////////////////////////////////////////////// // psHw Optimized Mappings // The HW Registers have been split into pages to improve optimization. // Anything not explicitly mapped into one of the hw_by_page handlers will be handled diff --git a/pcsx2/PrecompiledHeader.h b/pcsx2/PrecompiledHeader.h index f9bbbe979a..8e91ef6769 100644 --- a/pcsx2/PrecompiledHeader.h +++ b/pcsx2/PrecompiledHeader.h @@ -9,13 +9,13 @@ // disabled in release builds. :) #ifdef _MSC_VER -#ifdef PCSX2_DEVBUILD -# define _SECURE_SCL 1 -# define _SECURE_SCL_THROWS 1 # pragma warning(disable:4244) // disable warning C4244: '=' : conversion from 'big' to 'small', possible loss of data -#else -# define _SECURE_SCL 0 -#endif +# ifdef PCSX2_DEVBUILD +# define _SECURE_SCL 1 +# define _SECURE_SCL_THROWS 1 +# else +# define _SECURE_SCL 0 +# endif #endif #define NOMINMAX // Disables other libs inclusion of their own min/max macros (we use std instead) diff --git a/pcsx2/ps2/Iop/IopHwWrite.cpp b/pcsx2/ps2/Iop/IopHwWrite.cpp index c538ba52b4..24c5bb9ba8 100644 --- a/pcsx2/ps2/Iop/IopHwWrite.cpp +++ b/pcsx2/ps2/Iop/IopHwWrite.cpp @@ -23,6 +23,41 @@ namespace IopMemory { using namespace Internal; +// Template-compatible version of the psxHu macro. Used for writing. +#define psxHu(mem) (*(u32*)&psxH[(mem) & 0xffff]) + + +////////////////////////////////////////////////////////////////////////////////////////// +// +template< typename T > +static __forceinline void _generic_write( u32 addr, T val ) +{ + int bitsize = (sizeof(T) == 1) ? 8 : ( (sizeof(T) == 2) ? 16 : 32 ); + PSXHW_LOG( "HwWrite%d to %s, addr 0x%08x = 0x%08x\n", bitsize, _log_GetIopHwName(addr), addr, val ); + psxHu(addr) = val; +} + +void __fastcall iopHwWrite8_generic( u32 addr, u8 val ) { _generic_write( addr, val ); } +void __fastcall iopHwWrite16_generic( u32 addr, u16 val ) { _generic_write( addr, val ); } +void __fastcall iopHwWrite32_generic( u32 addr, u32 val ) { _generic_write( addr, val ); } + +////////////////////////////////////////////////////////////////////////////////////////// +// +template< typename T > +static __forceinline T _generic_read( u32 addr ) +{ + int bitsize = (sizeof(T) == 1) ? 8 : ( (sizeof(T) == 2) ? 16 : 32 ); + + T ret = psxHu(addr); + PSXHW_LOG( "HwRead%d from %s, addr 0x%08x = 0x%08x\n", bitsize, _log_GetIopHwName(addr), addr, ret ); + return ret; +} + +u8 __fastcall iopHwRead8_generic( u32 addr ) { return _generic_read( addr ); } +u16 __fastcall iopHwRead16_generic( u32 addr ) { return _generic_read( addr ); } +u32 __fastcall iopHwRead32_generic( u32 addr ) { return _generic_read( addr ); } + + ////////////////////////////////////////////////////////////////////////////////////////// // void __fastcall iopHwWrite8_Page1( u32 addr, u8 val ) @@ -116,9 +151,6 @@ void __fastcall iopHwWrite8_Page8( u32 addr, u8 val ) } -// Template-compatible version of the psxHu macro. Used for writing. -#define psxHu(mem) (*(u32*)&psxH[(mem) & 0xffff]) - ////////////////////////////////////////////////////////////////////////////////////////// // Templated handler for both 32 and 16 bit write operations, to Page 1 registers. // @@ -508,7 +540,6 @@ void __fastcall iopHwWrite32_Page8( u32 addr, u32 val ) else psxHu32(addr) = val; PSXHW_LOG( "HwWrite32 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName( addr ), addr, val ); - } } diff --git a/pcsx2/ps2/Iop/IopHw_Internal.h b/pcsx2/ps2/Iop/IopHw_Internal.h index 1a78d64bec..c15e7d9a0b 100644 --- a/pcsx2/ps2/Iop/IopHw_Internal.h +++ b/pcsx2/ps2/Iop/IopHw_Internal.h @@ -201,4 +201,4 @@ static __forceinline const char* _log_GetIopHwName( u32 addr ) } } -} }; \ No newline at end of file +} };