mirror of https://github.com/PCSX2/pcsx2.git
Some updates by Jake and 2 lines from me, hope this fixes savestates. Please test guys :)
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@359 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
ramapcsx2
Gregory Hainaut
parent
266875132d
commit
361afda5ed
125
pcsx2/Counters.c
125
pcsx2/Counters.c
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@ -83,14 +83,6 @@ static __forceinline void cpuRcntSet()
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nextsCounter = cpuRegs.cycle;
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nextCounter = (counters[5].sCycle + counters[5].CycleT) - cpuRegs.cycle;
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// if we're running behind, the diff will be negative.
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// (and running behind means we need to branch again ASAP)
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if( nextCounter <= 0 )
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{
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nextCounter = 0;
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return;
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}
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for (i = 0; i < 4; i++)
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_rcntSet( i );
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@ -487,7 +479,6 @@ static __forceinline void VSyncEnd(u32 sCycle) // VSync End
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hwIntcIrq(3); // HW Irq
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psxVBlankEnd(); // psxCounters vBlank End
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if (gates) rcntEndGate(0x8, sCycle); // Counters End Gate Code
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SysUpdate(); // check for and handle keyevents
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frameLimit(); // limit FPS (also handles frameskip and VUskip)
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}
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@ -542,6 +533,8 @@ __forceinline void rcntUpdate_vSync()
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counters[5].sCycle += vSyncInfo.Blank;
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counters[5].CycleT = vSyncInfo.Render;
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counters[5].mode = MODE_VRENDER;
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SysUpdate(); // check for and handle keyevents
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}
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else // VSYNC end / VRENDER begin
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{
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@ -570,7 +563,7 @@ __forceinline void rcntUpdate_vSync()
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static __forceinline void __fastcall _cpuTestTarget( int i )
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{
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//counters[i].target &= 0xffff;
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if (counters[i].count < counters[i].target) return;
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if(counters[i].mode & 0x100) {
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@ -586,6 +579,21 @@ static __forceinline void __fastcall _cpuTestTarget( int i )
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else counters[i].target |= 0x10000000;
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}
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static __forceinline void _cpuTestOverflow( int i )
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{
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if (counters[i].count <= 0xffff) return;
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if (counters[i].mode & 0x0200) { // Overflow interrupt
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EECNT_LOG("EE counter %d overflow mode %x count %x target %x\n", i, counters[i].mode, counters[i].count, counters[i].target);
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counters[i].mode |= 0x0800; // Overflow flag
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hwIntcIrq(counters[i].interrupt);
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}
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// wrap counter back around zero, and enable the future target:
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counters[i].count -= 0x10000;
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counters[i].target &= 0xffff;
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}
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// forceinline note: this method is called from two locations, but one
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// of them is the interpreter, which doesn't count. ;) So might as
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@ -596,14 +604,16 @@ __forceinline void rcntUpdate()
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rcntUpdate_vSync();
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// Update all counters?
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// This code shouldn't be needed. Counters are updated as needed when
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// Reads, Writes, and Target/Overflow events occur. The rest of the
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// time the counters can be left unmodified.
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// Update counters so that we can perform overflow and target tests.
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for (i=0; i<=3; i++) {
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if ( gates & (1<<i) ) continue;
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if ((counters[i].mode & 0x80) && (counters[i].mode & 0x3) != 0x3) {
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// We want to count gated counters (except the hblank which excluded below)
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//if ( gates & (1<<i) ) continue;
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if (!(counters[i].mode & 0x80)) continue;
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if((counters[i].mode & 0x3) != 0x3) { // don't count hblank sources
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s32 change = cpuRegs.cycle - counters[i].sCycleT;
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if( change > 0 ) {
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@ -621,26 +631,8 @@ __forceinline void rcntUpdate()
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{
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if (!(counters[i].mode & 0x80)) continue; // Stopped
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// Target reached?
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if (counters[i].count >= counters[i].target)
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_cpuTestTarget( i );
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if (counters[i].count > 0xffff) {
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if (counters[i].mode & 0x0200) { // Overflow interrupt
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EECNT_LOG("EE counter %d overflow mode %x count %x target %x\n", i, counters[i].mode, counters[i].count, counters[i].target);
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counters[i].mode |= 0x0800; // Overflow flag
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hwIntcIrq(counters[i].interrupt);
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}
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counters[i].count -= 0x10000;
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counters[i].target &= 0xffff;
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// Target reached after overflow?
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// It's possible that a Target very near zero (1-10, etc) could have already been reached.
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// Checking for it now
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//if (counters[i].count >= counters[i].target)
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// _cpuTestTarget( i );
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}
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_cpuTestTarget( i );
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_cpuTestOverflow( i );
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}
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cpuRcntSet();
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}
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@ -665,6 +657,21 @@ void rcntWcount(int index, u32 value)
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_rcntSet( index );
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}
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static void _rcntSetGate( int index )
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{
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if((counters[index].mode & 0xF) == 0x7) {
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gates &= ~(1<<index);
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SysPrintf("Counters: Gate Disabled\n");
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//counters[index].mode &= ~0x80;
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}
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else if (counters[index].mode & 0x4) {
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gates |= (1<<index);
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counters[index].mode &= ~0x80;
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rcntReset(index);
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}
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else gates &= ~(1<<index);
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}
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void rcntWmode(int index, u32 value)
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{
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if(counters[index].mode & 0x80) {
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@ -692,21 +699,11 @@ void rcntWmode(int index, u32 value)
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case 3: counters[index].rate = vSyncInfo.hBlank+vSyncInfo.hRender; break;
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}
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if((counters[index].mode & 0xF) == 0x7) {
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gates &= ~(1<<index);
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SysPrintf("Counters: Gate Disabled\n");
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//counters[index].mode &= ~0x80;
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}
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else if (counters[index].mode & 0x4) {
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gates |= (1<<index);
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counters[index].mode &= ~0x80;
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rcntReset(index);
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}
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else gates &= ~(1<<index);
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_rcntSetGate( index );
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_rcntSet( index );
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}
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// mode - 0 means hblank source, 8 means vblank source.
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void rcntStartGate(unsigned int mode, u32 sCycle) {
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int i;
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@ -749,6 +746,7 @@ void rcntStartGate(unsigned int mode, u32 sCycle) {
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// rcntUpdate, since we're being called from there anyway.
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}
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// mode - 0 means hblank signal, 8 means vblank signal.
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void rcntEndGate(unsigned int mode, u32 sCycle) {
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int i;
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@ -764,7 +762,7 @@ void rcntEndGate(unsigned int mode, u32 sCycle) {
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counters[i].count = rcntRcount(i);
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counters[i].mode &= ~0x80;
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counters[i].sCycleT = sCycle;
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break;
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case 0x10: // Reset and start counting on Vsync start
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// this is the vsync end so do nothing
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@ -825,22 +823,14 @@ u32 rcntCycle(int index) {
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int rcntFreeze(gzFile f, int Mode) {
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if( Mode == 1 )
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{
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// Temp Hack Fix: Adjust some values so that they'll load properly
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// in the future (this should be removed when a new savestate version
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// is introduced).
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counters[4].sCycle += vSyncInfo.hRender;
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counters[5].sCycle += vSyncInfo.Render;
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}
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gzfreezel(counters);
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gzfreeze(&nextCounter, sizeof(nextCounter));
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gzfreeze(&nextsCounter, sizeof(nextsCounter));
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if( Mode == 0 )
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{
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int i;
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// Sanity check for loading older savestates:
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if( counters[4].sCycle == 0 )
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@ -848,17 +838,14 @@ int rcntFreeze(gzFile f, int Mode) {
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if( counters[5].sCycle == 0 )
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counters[5].sCycle = cpuRegs.cycle;
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// make sure the gate flags are set based on the counter modes...
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for( i=0; i<4; i++ )
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_rcntSetGate( i );
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}
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// Old versions of PCSX2 saved the counters *after* incrementing them.
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// So if we don't roll back here, the counters move past cpuRegs.cycle
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// and everthing explodes!
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// Note: Roll back regardless of load or save, since we roll them forward
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// when saving (above). It's a hack, but it works.
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counters[4].sCycle -= vSyncInfo.hRender;
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counters[5].sCycle -= vSyncInfo.Render;
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iopBranchAction = 1; // probably not needed but won't hurt anything either.
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return 0;
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}
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@ -24,9 +24,10 @@
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typedef struct {
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u32 count, mode, target, hold;
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u32 rate, interrupt;
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u32 Cycle, sCycle;
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u32 Cycle;
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u32 sCycle; // start cycle of timer
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s32 CycleT;
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u32 sCycleT;
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u32 sCycleT; // delta values should be signed.
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} Counter;
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//------------------------------------------------------------------
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@ -485,6 +485,7 @@ int SaveState(const char *file) {
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gzwrite(f, &psxRegs.cycle, sizeof(u32)); // used to be IOPoCycle. This retains compatibility.
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gzwrite(f, &g_nextBranchCycle, sizeof(g_nextBranchCycle));
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gzwrite(f, &g_psxNextBranchCycle, sizeof(g_psxNextBranchCycle));
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gzwrite(f, &psxNextsCounter, sizeof(psxNextsCounter));
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gzwrite(f, &s_iLastCOP0Cycle, sizeof(s_iLastCOP0Cycle));
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gzwrite(f, s_iLastPERFCycle, sizeof(u32)*2);
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gzwrite(f, &g_psxWriteOk, sizeof(g_psxWriteOk));
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@ -616,6 +617,7 @@ int LoadState(const char *file) {
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gzread(f, &dud, sizeof(u32)); // was IOPoCycle
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gzread(f, &g_nextBranchCycle, sizeof(g_nextBranchCycle));
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gzread(f, &g_psxNextBranchCycle, sizeof(g_psxNextBranchCycle));
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gzread(f, &psxNextsCounter, sizeof(psxNextsCounter));
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gzread(f, &s_iLastCOP0Cycle, sizeof(s_iLastCOP0Cycle));
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if( dwCurSaveStateVer >= 0x7a30000e ) {
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gzread(f, s_iLastPERFCycle, sizeof(u32)*2);
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@ -27,8 +27,8 @@ u8 psxhblankgate = 0;
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u8 psxvblankgate = 0;
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u8 psxcntmask = 0;
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// flags when the gate is on (counting)
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#define IOPCNT_GATE_STOPPED (0x10000000ul)
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// flags when the gate is off or counter disabled. (do not count)
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#define IOPCNT_STOPPED (0x10000000ul)
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// used to disable targets until after an overflow
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#define IOPCNT_FUTURE_TARGET (0x1000000000ULL)
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@ -41,7 +41,7 @@ u8 psxcntmask = 0;
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// Use an arbitrary value to flag HBLANK counters.
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// These counters will be counted by the hblank gates coming from the EE,
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// which ensures they stay 100% in sync with the EE's hblank counters.
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#define PSXHBLANK 0x2000
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#define PSXHBLANK 0x2001
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static void psxRcntReset(int index)
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{
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@ -63,7 +63,7 @@ __forceinline static void _rcntSet( int i )
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// that into account. Adding the difference from that cycle count to the current one
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// will do the trick!
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if( psxCounters[i].mode & IOPCNT_GATE_STOPPED || psxCounters[i].rate == PSXHBLANK) return;
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if( psxCounters[i].mode & IOPCNT_STOPPED || psxCounters[i].rate == PSXHBLANK) return;
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c = (u64)((overflowCap - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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c += psxRegs.cycle - psxNextsCounter; // adjust for time passed since last rcntUpdate();
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@ -226,7 +226,7 @@ static void _psxCheckStartGate( int i )
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// get the current count at the time of stoppage:
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psxCounters[i].count = ( i < 3 ) ?
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psxRcntRcount16( i ) : psxRcntRcount32( i );
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psxCounters[i].mode |= IOPCNT_GATE_STOPPED;
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psxCounters[i].mode |= IOPCNT_STOPPED;
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return;
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case 0x1: //GATE_ON_ClearStart - count normally with resets after every end gate
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@ -236,7 +236,7 @@ static void _psxCheckStartGate( int i )
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case 0x2: //GATE_ON_Clear_OFF_Start - start counting on gate start, stop on gate end
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psxCounters[i].count = 0;
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxCounters[i].mode &= ~IOPCNT_GATE_STOPPED;
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psxCounters[i].mode &= ~IOPCNT_STOPPED;
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break;
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case 0x3: //GATE_ON_Start - start and count normally on gate end (no restarts or stops or clears)
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@ -256,21 +256,21 @@ static void _psxCheckEndGate(int i)
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case 0x1: //GATE_ON_ClearStart - count normally with resets after every end gate
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psxCounters[i].count = 0;
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxCounters[i].mode &= ~IOPCNT_GATE_STOPPED;
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psxCounters[i].mode &= ~IOPCNT_STOPPED;
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break;
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case 0x2: //GATE_ON_Clear_OFF_Start - start counting on gate start, stop on gate end
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psxCounters[i].count = ( i < 3 ) ?
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psxRcntRcount16( i ) : psxRcntRcount32( i );
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psxCounters[i].mode |= IOPCNT_GATE_STOPPED;
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psxCounters[i].mode |= IOPCNT_STOPPED;
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return; // do not set the counter
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case 0x3: //GATE_ON_Start - start and count normally (no restarts or stops or clears)
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if( psxCounters[i].mode & IOPCNT_GATE_STOPPED )
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if( psxCounters[i].mode & IOPCNT_STOPPED )
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{
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psxCounters[i].count = 0;
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxCounters[i].mode &= ~IOPCNT_GATE_STOPPED;
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psxCounters[i].mode &= ~IOPCNT_STOPPED;
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}
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break;
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}
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@ -289,7 +289,7 @@ void psxCheckStartGate16(int i)
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// We count them here so that they stay nicely synced with the EE's hsync.
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const u32 altSourceCheck = IOPCNT_ALT_SOURCE | IOPCNT_ENABLE_GATE;
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const u32 stoppedGateCheck = (IOPCNT_GATE_STOPPED | altSourceCheck );
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const u32 stoppedGateCheck = (IOPCNT_STOPPED | altSourceCheck );
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// count if alt source is enabled and either:
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// * the gate is enabled and not stopped.
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@ -364,7 +364,7 @@ void psxRcntUpdate()
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// We can't check the ALTSOURCE flag because the PSXCLOCK source *should*
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// be counted here.
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if( psxCounters[i].mode & (IOPCNT_GATE_STOPPED | IOPCNT_ENABLE_GATE) ) continue;
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if( psxCounters[i].mode & (IOPCNT_STOPPED | IOPCNT_ENABLE_GATE) ) continue;
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if( psxCounters[i].rate == PSXHBLANK ) continue;
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if( change <= 0 ) continue;
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@ -387,7 +387,7 @@ void psxRcntUpdate()
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// don't do target/oveflow checks for hblankers. Those
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// checks are done when the counters are updated.
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if( psxCounters[i].rate == PSXHBLANK ) continue;
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if( psxCounters[i].mode & IOPCNT_GATE_STOPPED ) continue;
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if( psxCounters[i].mode & IOPCNT_STOPPED ) continue;
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_rcntTestTarget( i );
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_rcntTestOverflow( i );
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@ -542,7 +542,7 @@ void psxRcnt2Wmode(u32 value)
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if((psxCounters[2].mode & 0x7) == 0x7 || (psxCounters[2].mode & 0x7) == 0x1)
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{
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//SysPrintf("Gate set on IOP C2, disabling\n");
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psxCounters[2].mode |= IOPCNT_GATE_STOPPED;
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psxCounters[2].mode |= IOPCNT_STOPPED;
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}
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psxCounters[2].count = 0;
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@ -593,7 +593,7 @@ void psxRcnt4Wmode(u32 value)
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if((psxCounters[4].mode & 0x7) == 0x7 || (psxCounters[4].mode & 0x7) == 0x1)
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{
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SysPrintf("Gate set on IOP C4, disabling\n");
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psxCounters[4].mode |= IOPCNT_GATE_STOPPED;
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psxCounters[4].mode |= IOPCNT_STOPPED;
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}
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psxCounters[4].count = 0;
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@ -620,7 +620,7 @@ void psxRcnt5Wmode(u32 value)
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if((psxCounters[5].mode & 0x7) == 0x7 || (psxCounters[5].mode & 0x7) == 0x1)
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{
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SysPrintf("Gate set on IOP C5, disabling\n");
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psxCounters[5].mode |= IOPCNT_GATE_STOPPED;
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psxCounters[5].mode |= IOPCNT_STOPPED;
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}
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psxCounters[5].count = 0;
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@ -673,7 +673,7 @@ u16 psxRcntRcount16(int index)
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// Don't count HBLANK timers
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// Don't count stopped gates either.
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if( !( psxCounters[index].mode & IOPCNT_GATE_STOPPED ) &&
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if( !( psxCounters[index].mode & IOPCNT_STOPPED ) &&
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( psxCounters[index].rate != PSXHBLANK ) )
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{
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u32 delta = (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
||||
|
|
@ -693,7 +693,7 @@ u32 psxRcntRcount32(int index)
|
|||
|
||||
PSXCNT_LOG("IOP Counter[%d] > readCount32 = %lx", index, retval );
|
||||
|
||||
if( !( psxCounters[index].mode & IOPCNT_GATE_STOPPED ) &&
|
||||
if( !( psxCounters[index].mode & IOPCNT_STOPPED ) &&
|
||||
( psxCounters[index].rate != PSXHBLANK ) )
|
||||
{
|
||||
u32 delta = (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
||||
|
|
@ -707,7 +707,7 @@ u32 psxRcntRcount32(int index)
|
|||
|
||||
u64 psxRcntCycles(int index)
|
||||
{
|
||||
if(psxCounters[index].mode & IOPCNT_GATE_STOPPED || psxCounters[index].rate == PSXHBLANK ) return psxCounters[index].count;
|
||||
if(psxCounters[index].mode & IOPCNT_STOPPED || psxCounters[index].rate == PSXHBLANK ) return psxCounters[index].count;
|
||||
return (u64)(psxCounters[index].count + (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate));
|
||||
}
|
||||
|
||||
|
|
@ -716,7 +716,7 @@ int psxRcntFreeze(gzFile f, int Mode)
|
|||
{
|
||||
if( Mode == 0 && (dwCurSaveStateVer < 0x7a300010) )
|
||||
{
|
||||
// --- Reading Mode ---
|
||||
// --- Reading Mode, Old Version ---
|
||||
// struct used to be 32bit count and target
|
||||
int i;
|
||||
u32 val;
|
||||
|
|
@ -731,16 +731,26 @@ int psxRcntFreeze(gzFile f, int Mode)
|
|||
else
|
||||
{
|
||||
gzfreezel(psxCounters);
|
||||
}
|
||||
|
||||
if( Mode == 0 )
|
||||
{
|
||||
// This is needed to make old save states compatible.
|
||||
psxCounters[6].rate = ((Config.Hacks & 0x4) ? 768 : (768*8));
|
||||
psxCounters[6].CycleT = psxCounters[6].rate;
|
||||
psxCounters[7].rate = PSXCLK/1000;
|
||||
psxCounters[7].CycleT = psxCounters[7].rate;
|
||||
if( Mode == 0 )
|
||||
{
|
||||
// This is needed to make old save states compatible.
|
||||
|
||||
psxCounters[6].rate = ((Config.Hacks & 0x4) ? 768 : (768*8));
|
||||
psxCounters[6].CycleT = psxCounters[6].rate;
|
||||
psxCounters[7].rate = PSXCLK/1000;
|
||||
psxCounters[7].CycleT = psxCounters[7].rate;
|
||||
|
||||
// PSXHBLANK is now an arbitrary value, since it can differ based
|
||||
// on PAL/NTSC and is timed by the EE.
|
||||
|
||||
if(psxCounters[1].mode & IOPCNT_ALT_SOURCE)
|
||||
psxCounters[1].rate = PSXHBLANK;
|
||||
|
||||
if(psxCounters[3].mode & IOPCNT_ALT_SOURCE)
|
||||
psxCounters[3].rate = PSXHBLANK;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
#ifndef __PSXCOUNTERS_H__
|
||||
#define __PSXCOUNTERS_H__
|
||||
|
||||
// fixme: sCycle and Cycle are unused.
|
||||
// fixme: sCycle, Cycle, and otarget are unused
|
||||
// Can't remove them without making a new savestate version though.
|
||||
|
||||
typedef struct {
|
||||
|
|
|
|||
Loading…
Reference in New Issue