From 2b8a808fe3ff475552f9f64906fb7e2664e366fb Mon Sep 17 00:00:00 2001 From: Gregory Hainaut Date: Tue, 29 Nov 2016 09:42:01 +0100 Subject: [PATCH] remove trailing white space (until I run clang-format on the full code) --- pcsx2/x86/newVif_Dynarec.cpp | 38 +++++++++--------- pcsx2/x86/newVif_UnpackSSE.cpp | 72 +++++++++++++++++----------------- 2 files changed, 55 insertions(+), 55 deletions(-) diff --git a/pcsx2/x86/newVif_Dynarec.cpp b/pcsx2/x86/newVif_Dynarec.cpp index 55e5cad14e..b9160f8ab3 100644 --- a/pcsx2/x86/newVif_Dynarec.cpp +++ b/pcsx2/x86/newVif_Dynarec.cpp @@ -79,10 +79,10 @@ __fi void VifUnpackSSE_Dynarec::SetMasks(int cS) const { const vifStruct& vif = MTVU_VifX; //This could have ended up copying the row when there was no row to write.1810080 - u32 m0 = vB.mask; //The actual mask example 0x03020100 + u32 m0 = vB.mask; //The actual mask example 0x03020100 u32 m3 = ((m0 & 0xaaaaaaaa)>>1) & ~m0; //all the upper bits, so our example 0x01010000 & 0xFCFDFEFF = 0x00010000 just the cols (shifted right for maskmerge) u32 m2 = (m0 & 0x55555555) & (~m0>>1); // 0x1000100 & 0xFE7EFF7F = 0x00000100 Just the row - + if((m2&&doMask)||doMode) { xMOVAPS(xmmRow, ptr128[&vif.MaskRow]); MSKPATH3_LOG("Moving row");} if (m3&&doMask) { MSKPATH3_LOG("Merging Cols"); @@ -97,10 +97,10 @@ __fi void VifUnpackSSE_Dynarec::SetMasks(int cS) const { void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const { pxAssertDev(regX.Id <= 1, "Reg Overflow! XMM2 thru XMM6 are reserved for masking."); - + int cc = aMin(vCL, 3); u32 m0 = (vB.mask >> (cc * 8)) & 0xff; //The actual mask example 0xE4 (protect, col, row, clear) - u32 m3 = ((m0 & 0xaa)>>1) & ~m0; //all the upper bits (cols shifted right) cancelling out any write protects 0x10 + u32 m3 = ((m0 & 0xaa)>>1) & ~m0; //all the upper bits (cols shifted right) cancelling out any write protects 0x10 u32 m2 = (m0 & 0x55) & (~m0>>1); // all the lower bits (rows)cancelling out any write protects 0x04 u32 m4 = (m0 & ~((m3<<1) | m2)) & 0x55; // = 0xC0 & 0x55 = 0x40 (for merge mask) @@ -110,15 +110,15 @@ void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const { if (doMask&&m2) { mergeVectors(regX, xmmRow, xmmTemp, m2); } // Merge MaskRow if (doMask&&m3) { mergeVectors(regX, xRegisterSSE(xmmCol0.Id+cc), xmmTemp, m3); } // Merge MaskCol - if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]); + if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]); mergeVectors(regX, xmmTemp, xmmTemp, m4); } // Merge Write Protect if (doMode) { u32 m5 = ~(m2|m3|m4) & 0xf; if (!doMask) m5 = 0xf; - if (m5 < 0xf) - { + if (m5 < 0xf) + { xPXOR(xmmTemp, xmmTemp); if (doMode == 3) { @@ -130,7 +130,7 @@ void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const { xPADD.D(regX, xmmTemp); if (doMode == 2) mergeVectors(xmmRow, regX, xmmTemp, m5); } - + } else { @@ -173,7 +173,7 @@ static void ShiftDisplacementWindow( xAddressVoid& addr, const xRegisterLong& mo void VifUnpackSSE_Dynarec::ModUnpack( int upknum, bool PostOp ) { - + switch( upknum ) { case 0: @@ -199,7 +199,7 @@ void VifUnpackSSE_Dynarec::ModUnpack( int upknum, bool PostOp ) pxFailRel( wxsFormat( L"Vpu/Vif - Invalid Unpack! [%d]", upknum ) ); break; } - + } void VifUnpackSSE_Dynarec::CompileRoutine() { const int upkNum = vB.upkType & 0xf; @@ -207,32 +207,32 @@ void VifUnpackSSE_Dynarec::CompileRoutine() { const int cycleSize = isFill ? vB.cl : vB.wl; const int blockSize = isFill ? vB.wl : vB.cl; const int skipSize = blockSize - cycleSize; - + uint vNum = vB.num ? vB.num : 256; doMode = (upkNum == 0xf) ? 0 : doMode; // V4_5 has no mode feature. UnpkNoOfIterations = 0; MSKPATH3_LOG("Compiling new block, unpack number %x, mode %x, masking %x, vNum %x", upkNum, doMode, doMask, vNum); - + pxAssume(vCL == 0); - + // Value passed determines # of col regs we need to load SetMasks(isFill ? blockSize : cycleSize); while (vNum) { - + ShiftDisplacementWindow( dstIndirect, ecx ); - if(UnpkNoOfIterations == 0) + if(UnpkNoOfIterations == 0) ShiftDisplacementWindow( srcIndirect, edx ); //Don't need to do this otherwise as we arent reading the source. - - + + if (vCL < cycleSize) { ModUnpack(upkNum, false); xUnpack(upkNum); xMovDest(); ModUnpack(upkNum, true); - + dstIndirect += 16; srcIndirect += vift; @@ -266,7 +266,7 @@ _vifT static __fi u8* dVifsetVUptr(uint cl, uint wl, bool isFill) { vifStruct& vif = MTVU_VifX; const VURegs& VU = vuRegs[idx]; const uint vuMemLimit = idx ? 0x4000 : 0x1000; - + u8* startmem = VU.Mem + (vif.tag.addr & (vuMemLimit-0x10)); u8* endmem = VU.Mem + vuMemLimit; uint length = (v.block.num > 0) ? (v.block.num * 16) : 4096; // 0 = 256 diff --git a/pcsx2/x86/newVif_UnpackSSE.cpp b/pcsx2/x86/newVif_UnpackSSE.cpp index acaba228f5..179e87cc3a 100644 --- a/pcsx2/x86/newVif_UnpackSSE.cpp +++ b/pcsx2/x86/newVif_UnpackSSE.cpp @@ -39,7 +39,7 @@ void mergeVectors(xRegisterSSE dest, xRegisterSSE src, xRegisterSSE temp, int xy || (xyzw==12) || (xyzw==11) || (xyzw==8) || (xyzw==3)) { mVUmergeRegs(dest, src, xyzw); } - else + else { if(temp != src) xMOVAPS(temp, src); //Sometimes we don't care if the source is modified and is temp reg. if(dest == temp) @@ -78,7 +78,7 @@ void VifUnpackSSE_Base::xShiftR(const xRegisterSSE& regX, int n) const { void VifUnpackSSE_Base::xPMOVXX8(const xRegisterSSE& regX) const { if (usn) xPMOVZX.BD(regX, ptr32[srcIndirect]); - else xPMOVSX.BD(regX, ptr32[srcIndirect]); + else xPMOVSX.BD(regX, ptr32[srcIndirect]); } void VifUnpackSSE_Base::xPMOVXX16(const xRegisterSSE& regX) const { @@ -88,8 +88,8 @@ void VifUnpackSSE_Base::xPMOVXX16(const xRegisterSSE& regX) const { void VifUnpackSSE_Base::xUPK_S_32() const { - switch(UnpkLoopIteration) - { + switch(UnpkLoopIteration) + { case 0: xMOV128 (workReg, ptr32[srcIndirect]); xPSHUF.D (destReg, workReg, _v0); @@ -104,12 +104,12 @@ void VifUnpackSSE_Base::xUPK_S_32() const { xPSHUF.D (destReg, workReg, _v3); break; } - + } void VifUnpackSSE_Base::xUPK_S_16() const { - if (!x86caps.hasStreamingSIMD4Extensions) + if (!x86caps.hasStreamingSIMD4Extensions) { xMOV16 (workReg, ptr32[srcIndirect]); xPUNPCK.LWD(workReg, workReg); @@ -119,8 +119,8 @@ void VifUnpackSSE_Base::xUPK_S_16() const { return; } - switch(UnpkLoopIteration) - { + switch(UnpkLoopIteration) + { case 0: xPMOVXX16 (workReg); xPSHUF.D (destReg, workReg, _v0); @@ -135,12 +135,12 @@ void VifUnpackSSE_Base::xUPK_S_16() const { xPSHUF.D (destReg, workReg, _v3); break; } - + } void VifUnpackSSE_Base::xUPK_S_8() const { - - if (!x86caps.hasStreamingSIMD4Extensions) + + if (!x86caps.hasStreamingSIMD4Extensions) { xMOV8 (workReg, ptr32[srcIndirect]); xPUNPCK.LBW(workReg, workReg); @@ -151,8 +151,8 @@ void VifUnpackSSE_Base::xUPK_S_8() const { return; } - switch(UnpkLoopIteration) - { + switch(UnpkLoopIteration) + { case 0: xPMOVXX8 (workReg); xPSHUF.D (destReg, workReg, _v0); @@ -167,7 +167,7 @@ void VifUnpackSSE_Base::xUPK_S_8() const { xPSHUF.D (destReg, workReg, _v3); break; } - + } // The V2 + V3 unpacks have freaky behaviour, the manual claims "indeterminate". @@ -177,19 +177,19 @@ void VifUnpackSSE_Base::xUPK_S_8() const { void VifUnpackSSE_Base::xUPK_V2_32() const { - if(UnpkLoopIteration == 0) - { + if(UnpkLoopIteration == 0) + { xMOV128 (workReg, ptr32[srcIndirect]); - xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0 + xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0 if(IsAligned)xAND.PS( destReg, ptr128[SSEXYZWMask[0]]); //zero last word - tested on ps2 } else { xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2 if(IsAligned)xAND.PS( destReg, ptr128[SSEXYZWMask[0]]); //zero last word - tested on ps2 - + } - + } void VifUnpackSSE_Base::xUPK_V2_16() const { @@ -199,7 +199,7 @@ void VifUnpackSSE_Base::xUPK_V2_16() const { if (x86caps.hasStreamingSIMD4Extensions) { xPMOVXX16 (workReg); - + } else { @@ -213,19 +213,19 @@ void VifUnpackSSE_Base::xUPK_V2_16() const { { xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2 } - - + + } void VifUnpackSSE_Base::xUPK_V2_8() const { if(UnpkLoopIteration == 0 || !x86caps.hasStreamingSIMD4Extensions) { - if (x86caps.hasStreamingSIMD4Extensions) + if (x86caps.hasStreamingSIMD4Extensions) { xPMOVXX8 (workReg); } - else + else { xMOV16 (workReg, ptr32[srcIndirect]); xPUNPCK.LBW(workReg, workReg); @@ -238,23 +238,23 @@ void VifUnpackSSE_Base::xUPK_V2_8() const { { xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2 } - + } void VifUnpackSSE_Base::xUPK_V3_32() const { xMOV128 (destReg, ptr128[srcIndirect]); - if(UnpkLoopIteration != IsAligned) + if(UnpkLoopIteration != IsAligned) xAND.PS( destReg, ptr128[SSEXYZWMask[0]]); } void VifUnpackSSE_Base::xUPK_V3_16() const { - if (x86caps.hasStreamingSIMD4Extensions) + if (x86caps.hasStreamingSIMD4Extensions) { xPMOVXX16 (destReg); } - else + else { xMOV64 (destReg, ptr32[srcIndirect]); xPUNPCK.LWD(destReg, destReg); @@ -270,15 +270,15 @@ void VifUnpackSSE_Base::xUPK_V3_16() const { if ((UnpkLoopIteration & 0x1) == 0 && result == 0){ xAND.PS(destReg, ptr128[SSEXYZWMask[0]]); //zero last word on QW boundary if whole 32bit word is used - tested on ps2 } -} +} void VifUnpackSSE_Base::xUPK_V3_8() const { - if (x86caps.hasStreamingSIMD4Extensions) + if (x86caps.hasStreamingSIMD4Extensions) { xPMOVXX8 (destReg); } - else + else { xMOV32 (destReg, ptr32[srcIndirect]); xPUNPCK.LBW(destReg, destReg); @@ -294,11 +294,11 @@ void VifUnpackSSE_Base::xUPK_V4_32() const { void VifUnpackSSE_Base::xUPK_V4_16() const { - if (x86caps.hasStreamingSIMD4Extensions) + if (x86caps.hasStreamingSIMD4Extensions) { xPMOVXX16 (destReg); } - else + else { xMOV64 (destReg, ptr32[srcIndirect]); xPUNPCK.LWD(destReg, destReg); @@ -308,11 +308,11 @@ void VifUnpackSSE_Base::xUPK_V4_16() const { void VifUnpackSSE_Base::xUPK_V4_8() const { - if (x86caps.hasStreamingSIMD4Extensions) + if (x86caps.hasStreamingSIMD4Extensions) { xPMOVXX8 (destReg); } - else + else { xMOV32 (destReg, ptr32[srcIndirect]); xPUNPCK.LBW(destReg, destReg); @@ -448,4 +448,4 @@ void VifUnpackSSE_Init() void VifUnpackSSE_Destroy() { safe_delete( nVifUpkExec ); -} \ No newline at end of file +}