ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Moved a few things around. Redid some of the work I did earlier on Hw with the non-obsolete version of the code. Changed some code not to use defines... 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1053 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-04-24 02:28:14 +00:00
parent e22a50a7c8
commit 286c405ce9
7 changed files with 337 additions and 186 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
common/include/Pcsx2Config.h
View File

@ -56,13 +56,20 @@ extern SessionOverrideFlags g_Session;
#define PCSX2_FRAMELIMIT_SKIP 0x800
#define PCSX2_FRAMELIMIT_VUSKIP 0xc00
#define CHECK_FRAMELIMIT (Config.Options&PCSX2_FRAMELIMIT_MASK)
//------------ CPU Options!!! ---------------
#define CHECK_MULTIGS (Config.Options&PCSX2_GSMULTITHREAD)
#define CHECK_EEREC (!g_Session.ForceDisableEErec && Config.Options&PCSX2_EEREC)
#define CHECK_VU0REC (!g_Session.ForceDisableVU0rec && Config.Options&PCSX2_VU0REC)
#define CHECK_VU1REC (!g_Session.ForceDisableVU1rec && (Config.Options&PCSX2_VU1REC))
//------------ SPECIAL GAME FIXES!!! ---------------
#define CHECK_VUADDSUBHACK (Config.GameFixes & 0x1) // Special Fix for Tri-ace games, they use an encryption algorithm that requires VU addi opcode to be bit-accurate.
#define CHECK_FPUCOMPAREHACK (Config.GameFixes & 0x4) // Special Fix for Digimon Rumble Arena 2, fixes spinning/hanging on intro-menu.
#define CHECK_VUCLIPFLAGHACK (Config.GameFixes & 0x2) // Special Fix for Persona games, maybe others. It's to do with the VU clip flag (again).
#define CHECK_FPUMULHACK (Config.GameFixes & 0x8) // Special Fix for Tales of Destiny hangs.
//------------ Advanced Options!!! ---------------
#define CHECK_VU_OVERFLOW (Config.vuOptions & 0x1)
#define CHECK_VU_EXTRA_OVERFLOW (Config.vuOptions & 0x2) // If enabled, Operands are clamped before being used in the VU recs
@ -75,14 +82,40 @@ extern SessionOverrideFlags g_Session;
#define CHECK_FPU_FULL (Config.eeOptions & 0x4)
#define DEFAULT_eeOptions 0x01
#define DEFAULT_vuOptions 0x01
//------------ DEFAULT sseMXCSR VALUES!!! ---------------
#define DEFAULT_sseMXCSR 0xffc0 //FPU rounding > DaZ, FtZ, "chop"
#define DEFAULT_sseVUMXCSR 0xffc0 //VU rounding > DaZ, FtZ, "chop"
#define CHECK_FRAMELIMIT (Config.Options&PCSX2_FRAMELIMIT_MASK)
//------------ Recompiler defines - Comment to disable a recompiler ---------------
// Yay! These work now! (air) ... almost (air)
#define CHECK_VU0REC (!g_Session.ForceDisableVU0rec && Config.Options&PCSX2_VU0REC)
#define CHECK_VU1REC (!g_Session.ForceDisableVU1rec && (Config.Options&PCSX2_VU1REC))
#define SHIFT_RECOMPILE // Speed majorly reduced if disabled
#define BRANCH_RECOMPILE // Speed extremely reduced if disabled - more then shift
// Disabling all the recompilers in this block is interesting, as it still runs at a reasonable rate.
// It also adds a few glitches. Really reminds me of the old Linux 64-bit version. --arcum42
#define ARITHMETICIMM_RECOMPILE
#define ARITHMETIC_RECOMPILE
#define MULTDIV_RECOMPILE
#define JUMP_RECOMPILE
#define LOADSTORE_RECOMPILE
#define MOVE_RECOMPILE
#define MMI_RECOMPILE
#define MMI0_RECOMPILE
#define MMI1_RECOMPILE
#define MMI2_RECOMPILE
#define MMI3_RECOMPILE
#define FPU_RECOMPILE
#define CP0_RECOMPILE
#define CP2_RECOMPILE
// You can't recompile ARITHMETICIMM without ARITHMETIC.
#ifndef ARITHMETIC_RECOMPILE
#undef ARITHMETICIMM_RECOMPILE
#endif
#define EE_CONST_PROP // rec2 - enables constant propagation (faster)
// Memory Card configuration, per slot.
struct McdConfig

12
pcsx2/Hw.cpp
View File

@ -149,8 +149,6 @@ int hwMFIFOWrite(u32 addr, u8 *data, u32 size) {
bool hwDmacSrcChainWithStack(DMACh *dma, int id) {
u32 temp;
switch (id) {
case 0: // Refe - Transfer Packet According to ADDR field
return true; //End Transfer
@ -161,18 +159,20 @@ bool hwDmacSrcChainWithStack(DMACh *dma, int id) {
return false;
case 2: // Next - Transfer QWC following tag. TADR = ADDR
temp = dma->madr; //Temporarily Store ADDR
{
u32 temp = dma->madr; //Temporarily Store ADDR
dma->madr = dma->tadr + 16; //Set MADR to QW following the tag
dma->tadr = temp; //Copy temporarily stored ADDR to Tag
return false;
}
case 3: // Ref - Transfer QWC from ADDR field
case 4: // Refs - Transfer QWC from ADDR field (Stall Control)
dma->tadr += 16; //Set TADR to next tag
return false;
case 5: // Call - Transfer QWC following the tag, save succeeding tag
temp = dma->madr; //Temporarily Store ADDR
{
u32 temp = dma->madr; //Temporarily Store ADDR
dma->madr = dma->tadr + 16; //Set MADR to data following the tag
@ -190,7 +190,7 @@ bool hwDmacSrcChainWithStack(DMACh *dma, int id) {
dma->tadr = temp; //Set TADR to temporarily stored ADDR
return false;
}
case 6: // Ret - Transfer QWC following the tag, load next tag
dma->madr = dma->tadr + 16; //Set MADR to data following the tag

63
pcsx2/HwRead.cpp
View File

@ -61,34 +61,35 @@ __forceinline u8 hwRead8(u32 mem)
switch (mem)
{
case 0x10000000: ret = (u8)rcntRcount(0); break;
case 0x10000010: ret = (u8)counters[0].modeval; break;
case 0x10000020: ret = (u8)counters[0].target; break;
case 0x10000030: ret = (u8)counters[0].hold; break;
// Note: the values without defines = the defines + 1.
case RCNT0_COUNT: ret = (u8)rcntRcount(0); break;
case RCNT0_MODE: ret = (u8)counters[0].modeval; break;
case RCNT0_TARGET: ret = (u8)counters[0].target; break;
case RCNT0_HOLD: ret = (u8)counters[0].hold; break;
case 0x10000001: ret = (u8)(rcntRcount(0)>>8); break;
case 0x10000011: ret = (u8)(counters[0].modeval>>8); break;
case 0x10000021: ret = (u8)(counters[0].target>>8); break;
case 0x10000031: ret = (u8)(counters[0].hold>>8); break;
case 0x10000800: ret = (u8)rcntRcount(1); break;
case 0x10000810: ret = (u8)counters[1].modeval; break;
case 0x10000820: ret = (u8)counters[1].target; break;
case 0x10000830: ret = (u8)counters[1].hold; break;
case RCNT1_COUNT: ret = (u8)rcntRcount(1); break;
case RCNT1_MODE: ret = (u8)counters[1].modeval; break;
case RCNT1_TARGET: ret = (u8)counters[1].target; break;
case RCNT1_HOLD: ret = (u8)counters[1].hold; break;
case 0x10000801: ret = (u8)(rcntRcount(1)>>8); break;
case 0x10000811: ret = (u8)(counters[1].modeval>>8); break;
case 0x10000821: ret = (u8)(counters[1].target>>8); break;
case 0x10000831: ret = (u8)(counters[1].hold>>8); break;
case 0x10001000: ret = (u8)rcntRcount(2); break;
case 0x10001010: ret = (u8)counters[2].modeval; break;
case 0x10001020: ret = (u8)counters[2].target; break;
case RCNT2_COUNT: ret = (u8)rcntRcount(2); break;
case RCNT2_MODE: ret = (u8)counters[2].modeval; break;
case RCNT2_TARGET: ret = (u8)counters[2].target; break;
case 0x10001001: ret = (u8)(rcntRcount(2)>>8); break;
case 0x10001011: ret = (u8)(counters[2].modeval>>8); break;
case 0x10001021: ret = (u8)(counters[2].target>>8); break;
case 0x10001800: ret = (u8)rcntRcount(3); break;
case 0x10001810: ret = (u8)counters[3].modeval; break;
case 0x10001820: ret = (u8)counters[3].target; break;
case RCNT3_COUNT: ret = (u8)rcntRcount(3); break;
case RCNT3_MODE: ret = (u8)counters[3].modeval; break;
case RCNT3_TARGET: ret = (u8)counters[3].target; break;
case 0x10001801: ret = (u8)(rcntRcount(3)>>8); break;
case 0x10001811: ret = (u8)(counters[3].modeval>>8); break;
case 0x10001821: ret = (u8)(counters[3].target>>8); break;
@ -97,7 +98,7 @@ __forceinline u8 hwRead8(u32 mem)
if ((mem & 0xffffff0f) == 0x1000f200)
{
if(mem == 0x1000f260) ret = 0;
else if(mem == 0x1000F240) {
else if(mem == SBUS_F240) {
ret = psHu32(mem);
//psHu32(mem) &= ~0x4000;
}
@ -120,34 +121,34 @@ __forceinline u16 hwRead16(u32 mem)
{
u16 ret;
if( mem >= 0x10002000 && mem < 0x10008000 )
if( mem >= IPU_CMD && mem < D0_CHCR )
Console::Notice("Unexpected hwRead16 from 0x%x", params mem);
switch (mem)
{
case 0x10000000: ret = (u16)rcntRcount(0); break;
case 0x10000010: ret = (u16)counters[0].modeval; break;
case 0x10000020: ret = (u16)counters[0].target; break;
case 0x10000030: ret = (u16)counters[0].hold; break;
case RCNT0_COUNT: ret = (u16)rcntRcount(0); break;
case RCNT0_MODE: ret = (u16)counters[0].modeval; break;
case RCNT0_TARGET: ret = (u16)counters[0].target; break;
case RCNT0_HOLD: ret = (u16)counters[0].hold; break;
case 0x10000800: ret = (u16)rcntRcount(1); break;
case 0x10000810: ret = (u16)counters[1].modeval; break;
case 0x10000820: ret = (u16)counters[1].target; break;
case 0x10000830: ret = (u16)counters[1].hold; break;
case RCNT1_COUNT: ret = (u16)rcntRcount(1); break;
case RCNT1_MODE: ret = (u16)counters[1].modeval; break;
case RCNT1_TARGET: ret = (u16)counters[1].target; break;
case RCNT1_HOLD: ret = (u16)counters[1].hold; break;
case 0x10001000: ret = (u16)rcntRcount(2); break;
case 0x10001010: ret = (u16)counters[2].modeval; break;
case 0x10001020: ret = (u16)counters[2].target; break;
case RCNT2_COUNT: ret = (u16)rcntRcount(2); break;
case RCNT2_MODE: ret = (u16)counters[2].modeval; break;
case RCNT2_TARGET: ret = (u16)counters[2].target; break;
case 0x10001800: ret = (u16)rcntRcount(3); break;
case 0x10001810: ret = (u16)counters[3].modeval; break;
case 0x10001820: ret = (u16)counters[3].target; break;
case RCNT3_COUNT: ret = (u16)rcntRcount(3); break;
case RCNT3_MODE: ret = (u16)counters[3].modeval; break;
case RCNT3_TARGET: ret = (u16)counters[3].target; break;
default:
if ((mem & 0xffffff0f) == 0x1000f200)
{
if(mem == 0x1000f260) ret = 0;
else if(mem == 0x1000F240) {
else if(mem == SBUS_F240) {
ret = psHu16(mem) | 0x0102;
psHu32(mem) &= ~0x4000;
}

148
pcsx2/HwWrite.cpp
View File

@ -145,27 +145,27 @@ void hwWrite8(u32 mem, u8 value) {
DevCon::Notice( "hwWrite8 to 0x%x = 0x%x", params mem, value );
switch (mem) {
case 0x10000000: rcntWcount(0, value); break;
case 0x10000010: rcntWmode(0, (counters[0].modeval & 0xff00) | value); break;
case RCNT0_COUNT: rcntWcount(0, value); break;
case RCNT0_MODE: rcntWmode(0, (counters[0].modeval & 0xff00) | value); break;
case 0x10000011: rcntWmode(0, (counters[0].modeval & 0xff) | value << 8); break;
case 0x10000020: rcntWtarget(0, value); break;
case 0x10000030: rcntWhold(0, value); break;
case RCNT0_TARGET: rcntWtarget(0, value); break;
case RCNT0_HOLD: rcntWhold(0, value); break;
case 0x10000800: rcntWcount(1, value); break;
case 0x10000810: rcntWmode(1, (counters[1].modeval & 0xff00) | value); break;
case RCNT1_COUNT: rcntWcount(1, value); break;
case RCNT1_MODE: rcntWmode(1, (counters[1].modeval & 0xff00) | value); break;
case 0x10000811: rcntWmode(1, (counters[1].modeval & 0xff) | value << 8); break;
case 0x10000820: rcntWtarget(1, value); break;
case 0x10000830: rcntWhold(1, value); break;
case RCNT1_TARGET: rcntWtarget(1, value); break;
case RCNT1_HOLD: rcntWhold(1, value); break;
case 0x10001000: rcntWcount(2, value); break;
case 0x10001010: rcntWmode(2, (counters[2].modeval & 0xff00) | value); break;
case RCNT2_COUNT: rcntWcount(2, value); break;
case RCNT2_MODE: rcntWmode(2, (counters[2].modeval & 0xff00) | value); break;
case 0x10001011: rcntWmode(2, (counters[2].modeval & 0xff) | value << 8); break;
case 0x10001020: rcntWtarget(2, value); break;
case RCNT2_TARGET: rcntWtarget(2, value); break;
case 0x10001800: rcntWcount(3, value); break;
case 0x10001810: rcntWmode(3, (counters[3].modeval & 0xff00) | value); break;
case RCNT3_COUNT: rcntWcount(3, value); break;
case RCNT3_MODE: rcntWmode(3, (counters[3].modeval & 0xff00) | value); break;
case 0x10001811: rcntWmode(3, (counters[3].modeval & 0xff) | value << 8); break;
case 0x10001820: rcntWtarget(3, value); break;
case RCNT3_TARGET: rcntWtarget(3, value); break;
case 0x1000f180:
if (value == '\n') {
@ -321,25 +321,25 @@ __forceinline void hwWrite16(u32 mem, u16 value)
switch(mem)
{
case 0x10000000: rcntWcount(0, value); break;
case 0x10000010: rcntWmode(0, value); break;
case 0x10000020: rcntWtarget(0, value); break;
case 0x10000030: rcntWhold(0, value); break;
case RCNT0_COUNT: rcntWcount(0, value); break;
case RCNT0_MODE: rcntWmode(0, value); break;
case RCNT0_TARGET: rcntWtarget(0, value); break;
case RCNT0_HOLD: rcntWhold(0, value); break;
case 0x10000800: rcntWcount(1, value); break;
case 0x10000810: rcntWmode(1, value); break;
case 0x10000820: rcntWtarget(1, value); break;
case 0x10000830: rcntWhold(1, value); break;
case RCNT1_COUNT: rcntWcount(1, value); break;
case RCNT1_MODE: rcntWmode(1, value); break;
case RCNT1_TARGET: rcntWtarget(1, value); break;
case RCNT1_HOLD: rcntWhold(1, value); break;
case 0x10001000: rcntWcount(2, value); break;
case 0x10001010: rcntWmode(2, value); break;
case 0x10001020: rcntWtarget(2, value); break;
case RCNT2_COUNT: rcntWcount(2, value); break;
case RCNT2_MODE: rcntWmode(2, value); break;
case RCNT2_TARGET: rcntWtarget(2, value); break;
case 0x10001800: rcntWcount(3, value); break;
case 0x10001810: rcntWmode(3, value); break;
case 0x10001820: rcntWtarget(3, value); break;
case RCNT3_COUNT: rcntWcount(3, value); break;
case RCNT3_MODE: rcntWmode(3, value); break;
case RCNT3_TARGET: rcntWtarget(3, value); break;
case 0x10008000: // dma0 - vif0
case D0_CHCR: // dma0 - vif0
DMA_LOG("VIF0dma %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -349,7 +349,7 @@ __forceinline void hwWrite16(u32 mem, u16 value)
DmaExec16(dmaVIF0, mem, value);
break;
case 0x10009000: // dma1 - vif1 - chcr
case D1_CHCR: // dma1 - vif1 - chcr
DMA_LOG("VIF1dma CHCR %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -361,34 +361,34 @@ __forceinline void hwWrite16(u32 mem, u16 value)
break;
#ifdef PCSX2_DEVBUILD
case 0x10009010: // dma1 - vif1 - madr
case D1_MADR: // dma1 - vif1 - madr
HW_LOG("VIF1dma Madr %lx", value);
psHu16(mem) = value;//dma1 madr
break;
case 0x10009020: // dma1 - vif1 - qwc
case D1_QWC: // dma1 - vif1 - qwc
HW_LOG("VIF1dma QWC %lx", value);
psHu16(mem) = value;//dma1 qwc
break;
case 0x10009030: // dma1 - vif1 - tadr
case D1_TADR: // dma1 - vif1 - tadr
HW_LOG("VIF1dma TADR %lx", value);
psHu16(mem) = value;//dma1 tadr
break;
case 0x10009040: // dma1 - vif1 - asr0
case D1_ASR0: // dma1 - vif1 - asr0
HW_LOG("VIF1dma ASR0 %lx", value);
psHu16(mem) = value;//dma1 asr0
break;
case 0x10009050: // dma1 - vif1 - asr1
case D1_ASR1: // dma1 - vif1 - asr1
HW_LOG("VIF1dma ASR1 %lx", value);
psHu16(mem) = value;//dma1 asr1
break;
case 0x10009080: // dma1 - vif1 - sadr
case D1_SADR: // dma1 - vif1 - sadr
HW_LOG("VIF1dma SADR %lx", value);
psHu16(mem) = value;//dma1 sadr
break;
#endif
// ---------------------------------------------------
case 0x1000a000: // dma2 - gif
case D2_CHCR: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx", cpuRegs.cycle, value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -399,33 +399,33 @@ __forceinline void hwWrite16(u32 mem, u16 value)
break;
#ifdef PCSX2_DEVBUILD
case 0x1000a010:
case D2_MADR:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000a020:
case D2_QWC:
psHu16(mem) = value;//dma2 qwc
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000a030:
case D2_TADR:
psHu16(mem) = value;//dma2 taddr
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value);
break;
case 0x1000a040:
case D2_ASR0:
psHu16(mem) = value;//dma2 asr0
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value);
break;
case 0x1000a050:
case D2_ASR1:
psHu16(mem) = value;//dma2 asr1
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value);
break;
case 0x1000a080:
case D2_SADR:
psHu16(mem) = value;//dma2 saddr
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000b000: // dma3 - fromIPU
case D3_CHCR: // dma3 - fromIPU
DMA_LOG("IPU0dma %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -436,25 +436,25 @@ __forceinline void hwWrite16(u32 mem, u16 value)
break;
#ifdef PCSX2_DEVBUILD
case 0x1000b010:
case D3_MADR:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b020:
case D3_QWC:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b030:
case D3_TADR:
psHu16(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b080:
case D3_SADR:
psHu16(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000b400: // dma4 - toIPU
case D4_CHCR: // dma4 - toIPU
DMA_LOG("IPU1dma %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -465,24 +465,24 @@ __forceinline void hwWrite16(u32 mem, u16 value)
break;
#ifdef PCSX2_DEVBUILD
case 0x1000b410:
case D4_MADR:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b420:
case D4_QWC:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b430:
case D4_TADR:
psHu16(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b480:
case D4_SADR:
psHu16(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000c000: // dma5 - sif0
case D5_CHCR: // dma5 - sif0
DMA_LOG("SIF0dma %lx", value);
// if (value == 0) psxSu32(0x30) = 0x40000;
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
@ -496,7 +496,7 @@ __forceinline void hwWrite16(u32 mem, u16 value)
case 0x1000c002:
//?
break;
case 0x1000c400: // dma6 - sif1
case D6_CHCR: // dma6 - sif1
DMA_LOG("SIF1dma %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -507,7 +507,8 @@ __forceinline void hwWrite16(u32 mem, u16 value)
break;
#ifdef PCSX2_DEVBUILD
case 0x1000c420: // dma6 - sif1 - qwc
// No D6_MADR, and a TADR address that's not in the defines?
case D6_QWC: // dma6 - sif1 - qwc
HW_LOG("SIF1dma QWC = %lx", value);
psHu16(mem) = value;
break;
@ -518,7 +519,7 @@ __forceinline void hwWrite16(u32 mem, u16 value)
break;
#endif
case 0x1000c800: // dma7 - sif2
case D7_CHCR: // dma7 - sif2
DMA_LOG("SIF2dma %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -530,7 +531,7 @@ __forceinline void hwWrite16(u32 mem, u16 value)
case 0x1000c802:
//?
break;
case 0x1000d000: // dma8 - fromSPR
case D8_CHCR: // dma8 - fromSPR
DMA_LOG("fromSPRdma %lx", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -565,13 +566,13 @@ __forceinline void hwWrite16(u32 mem, u16 value)
psHu16(mem) = value;
break;
case 0x1000f220:
case SBUS_F220:
psHu16(mem) |= value;
break;
case 0x1000f230:
case SBUS_SMFLG:
psHu16(mem) &= ~value;
break;
case 0x1000f240:
case SBUS_F240:
if(!(value & 0x100))
psHu16(mem) &= ~0x100;
else
@ -795,13 +796,13 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value )
case HELPSWITCH(0x1000f200):
psHu32(mem) = value;
break;
case HELPSWITCH(0x1000f220):
case HELPSWITCH(SBUS_F220):
psHu32(mem) |= value;
break;
case HELPSWITCH(0x1000f230):
case HELPSWITCH(SBUS_SMFLG):
psHu32(mem) &= ~value;
break;
case HELPSWITCH(0x1000f240):
case HELPSWITCH(SBUS_F240):
if(!(value & 0x100))
psHu32(mem) &= ~0x100;
else
@ -815,7 +816,7 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value )
psHu32(mem) = value;
break;
case HELPSWITCH(0x1000f590): // DMAC_ENABLEW
case HELPSWITCH(DMAC_ENABLEW): // DMAC_ENABLEW
HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
psHu32(0xf590) = value;
psHu32(0xf520) = value;
@ -890,7 +891,7 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
case D2_SADR: regName = "GIFdma SADDR"; break;
//------------------------------------------------------------------
case 0x1000c000: // dma5 - sif0
case D5_CHCR: // dma5 - sif0
DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
//if (value == 0) psxSu32(0x30) = 0x40000;
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
@ -901,7 +902,7 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
DmaExec(dmaSIF0, mem, value);
return;
//------------------------------------------------------------------
case 0x1000c400: // dma6 - sif1
case D6_CHCR: // dma6 - sif1
DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -911,11 +912,12 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
DmaExec(dmaSIF1, mem, value);
return;
case 0x1000c420: regName = "SIF1dma QWC"; break;
// Again, no MADR, and an undefined TADR.
case D6_QWC: regName = "SIF1dma QWC"; break;
case 0x1000c430: regName = "SIF1dma TADR"; break;
//------------------------------------------------------------------
case 0x1000c800: // dma7 - sif2
case D7_CHCR: // dma7 - sif2
DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -925,7 +927,7 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
DmaExec(dmaSIF2, mem, value);
return;
//------------------------------------------------------------------
case 0x1000d000: // dma8 - fromSPR
case D8_CHCR: // dma8 - fromSPR
DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1))
{
@ -1048,7 +1050,7 @@ void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval )
switch (mem)
{
case 0x1000a000: // dma2 - gif
case D2_CHCR: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite64: GSdma %x", cpuRegs.cycle, value);
DmaExec(dmaGIF, mem, value);
break;
@ -1070,7 +1072,7 @@ void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval )
case 0x1000f430:
break;
case 0x1000f590: // DMAC_ENABLEW
case DMAC_ENABLEW: // DMAC_ENABLEW
psHu32(0xf590) = value;
psHu32(0xf520) = value;
break;
@ -1103,7 +1105,7 @@ void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval)
cpuTestINTCInts();
break;
case 0x1000f590: // DMAC_ENABLEW
case DMAC_ENABLEW: // DMAC_ENABLEW
psHu32(0xf590) = srcval[0];
psHu32(0xf520) = srcval[0];
break;

236
pcsx2/Interpreter.cpp
View File

@ -112,7 +112,8 @@ void __fastcall intDoBranch(u32 target)
}
}
void intSetBranch() {
void intSetBranch()
{
branch2 = /*cpuRegs.branch =*/ 1;
}
@ -133,90 +134,223 @@ namespace OpcodeImpl {
* Format: OP target *
*********************************************************/
void J() {
void J()
{
doBranch(_JumpTarget_);
}
void JAL() {
_SetLink(31); doBranch(_JumpTarget_);
void JAL()
{
_SetLink(31);
doBranch(_JumpTarget_);
}
/*********************************************************
* Register branch logic *
* Format: OP rs, rt, offset *
*********************************************************/
#define RepBranchi32(op) \
if (cpuRegs.GPR.r[_Rs_].SD[0] op cpuRegs.GPR.r[_Rt_].SD[0]) doBranch(_BranchTarget_); \
else intEventTest();
void BEQ() // Branch if Rs == Rt
{
if (cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0])
doBranch(_BranchTarget_);
else
intEventTest();
}
void BEQ() { RepBranchi32(==) } // Branch if Rs == Rt
void BNE() { RepBranchi32(!=) } // Branch if Rs != Rt
void BNE() // Branch if Rs != Rt
{
if (cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0])
doBranch(_BranchTarget_);
else
intEventTest();
}
/*********************************************************
* Register branch logic *
* Format: OP rs, offset *
*********************************************************/
#define RepZBranchi32(op) \
if(cpuRegs.GPR.r[_Rs_].SD[0] op 0) { \
doBranch(_BranchTarget_); \
}
#define RepZBranchLinki32(op) \
void BGEZ() // Branch if Rs >= 0
{
if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
{
doBranch(_BranchTarget_);
}
}
void BGEZAL() // Branch if Rs >= 0 and link
{
_SetLink(31);
if (cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
{
doBranch(_BranchTarget_);
}
}
void BGTZ() // Branch if Rs > 0
{
if (cpuRegs.GPR.r[_Rs_].SD[0] > 0)
{
doBranch(_BranchTarget_);
}
}
void BLEZ() // Branch if Rs <= 0
{
if (cpuRegs.GPR.r[_Rs_].SD[0] <= 0)
{
doBranch(_BranchTarget_);
}
}
void BLTZ() // Branch if Rs < 0
{
if (cpuRegs.GPR.r[_Rs_].SD[0] < 0)
{
doBranch(_BranchTarget_);
}
}
void BLTZAL() // Branch if Rs < 0 and link
{
_SetLink(31); \
if(cpuRegs.GPR.r[_Rs_].SD[0] op 0) { \
doBranch(_BranchTarget_); \
if (cpuRegs.GPR.r[_Rs_].SD[0] < 0)
{
doBranch(_BranchTarget_);
}
void BGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0
void BGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
void BGTZ() { RepZBranchi32(>) } // Branch if Rs > 0
void BLEZ() { RepZBranchi32(<=) } // Branch if Rs <= 0
void BLTZ() { RepZBranchi32(<) } // Branch if Rs < 0
void BLTZAL() { RepZBranchLinki32(<) } // Branch if Rs < 0 and link
}
/*********************************************************
* Register branch logic Likely *
* Format: OP rs, offset *
*********************************************************/
#define RepZBranchi32Likely(op) \
if(cpuRegs.GPR.r[_Rs_].SD[0] op 0) { \
doBranch(_BranchTarget_); \
} else { cpuRegs.pc +=4; intEventTest(); }
#define RepZBranchLinki32Likely(op) \
_SetLink(31); \
if(cpuRegs.GPR.r[_Rs_].SD[0] op 0) { \
doBranch(_BranchTarget_); \
} else { cpuRegs.pc +=4; intEventTest(); }
#define RepBranchi32Likely(op) \
if(cpuRegs.GPR.r[_Rs_].SD[0] op cpuRegs.GPR.r[_Rt_].SD[0]) { \
doBranch(_BranchTarget_); \
} else { cpuRegs.pc +=4; intEventTest(); }
void BEQL() { RepBranchi32Likely(==) } // Branch if Rs == Rt
void BNEL() { RepBranchi32Likely(!=) } // Branch if Rs != Rt
void BLEZL() { RepZBranchi32Likely(<=) } // Branch if Rs <= 0
void BGTZL() { RepZBranchi32Likely(>) } // Branch if Rs > 0
void BLTZL() { RepZBranchi32Likely(<) } // Branch if Rs < 0
void BGEZL() { RepZBranchi32Likely(>=) } // Branch if Rs >= 0
void BLTZALL() { RepZBranchLinki32Likely(<) } // Branch if Rs < 0 and link
void BGEZALL() { RepZBranchLinki32Likely(>=) } // Branch if Rs >= 0 and link
void BEQL() // Branch if Rs == Rt
{
if(cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0])
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BNEL() // Branch if Rs != Rt
{
if(cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0])
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BLEZL() // Branch if Rs <= 0
{
if(cpuRegs.GPR.r[_Rs_].SD[0] <= 0)
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BGTZL() // Branch if Rs > 0
{
if(cpuRegs.GPR.r[_Rs_].SD[0] > 0)
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BLTZL() // Branch if Rs < 0
{
if(cpuRegs.GPR.r[_Rs_].SD[0] < 0)
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BGEZL() // Branch if Rs >= 0
{
if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BLTZALL() // Branch if Rs < 0 and link
{
_SetLink(31);
if(cpuRegs.GPR.r[_Rs_].SD[0] < 0)
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
void BGEZALL() // Branch if Rs >= 0 and link
{
_SetLink(31);
if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
{
doBranch(_BranchTarget_);
}
else
{
cpuRegs.pc +=4;
intEventTest();
}
}
/*********************************************************
* Register jump *
* Format: OP rs, rd *
*********************************************************/
void JR() {
void JR()
{
doBranch(cpuRegs.GPR.r[_Rs_].UL[0]);
}
void JALR() {
void JALR()
{
u32 temp = cpuRegs.GPR.r[_Rs_].UL[0];
if (_Rd_) { _SetLink(_Rd_); }
if (_Rd_) _SetLink(_Rd_);
doBranch(temp);
}
@ -235,7 +369,7 @@ void intReset()
branch2 = 0;
}
bool intEventTest()
bool intEventTest()
{
// Perform counters, ints, and IOP updates:
return _cpuBranchTest_Shared();

4
pcsx2/x86/iMMI.cpp
View File

@ -273,7 +273,7 @@ void recPMTHL()
}
// MMX helper routines
#define MMX_ALLOC_TEMP1(code) { \
/*#define MMX_ALLOC_TEMP1(code) { \
int t0reg; \
t0reg = _allocMMXreg(-1, MMX_TEMP, 0); \
code; \
@ -311,7 +311,7 @@ void recPMTHL()
_freeMMXreg(t1reg); \
_freeMMXreg(t2reg); \
_freeMMXreg(t3reg); \
} \
} \*/
////////////////////////////////////////////////////
void recPSRLH( void )

21
pcsx2/x86/iR5900.h
View File

@ -24,26 +24,7 @@
#include "R5900.h"
#include "VU.h"
#include "iCore.h"
// Yay! These work now! (air) ... almost (air)
#define ARITHMETICIMM_RECOMPILE
#define ARITHMETIC_RECOMPILE
#define MULTDIV_RECOMPILE
#define SHIFT_RECOMPILE
#define BRANCH_RECOMPILE
#define JUMP_RECOMPILE
#define LOADSTORE_RECOMPILE
#define MOVE_RECOMPILE
#define MMI_RECOMPILE
#define MMI0_RECOMPILE
#define MMI1_RECOMPILE
#define MMI2_RECOMPILE
#define MMI3_RECOMPILE
#define FPU_RECOMPILE
#define CP0_RECOMPILE
#define CP2_RECOMPILE
#define EE_CONST_PROP // rec2 - enables constant propagation (faster)
#include "Pcsx2Config.h"
#define PC_GETBLOCK(x) PC_GETBLOCK_(x, recLUT)