mirror of https://github.com/PCSX2/pcsx2.git
Improved PCR/TIMR support -- fixed a case where games would try and read from the PCR multiple times in the same recompiled block, reuslting in bogus values, and fixed some sign extension errors on the interpreted version of MFC0.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@738 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
cef77785cb
commit
15901551b4
146
pcsx2/COP0.cpp
146
pcsx2/COP0.cpp
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@ -144,79 +144,137 @@ void WriteTLB(int i)
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MapTLB(i);
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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// Note regarding updates of PERF and TIMR registers: never allow increment to be 0.
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// That happens when a game loads the MFC0 twice in the same recompiled block (before the
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// cpuRegs.cycles update), and can cause games to lock up since it's an unexpected result.
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__forceinline void COP0_UpdatePCR0()
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{
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020)
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{
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u32 incr = cpuRegs.cycle-s_iLastPERFCycle[0];
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if( incr == 0 ) incr++;
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cpuRegs.PERF.n.pcr0 += incr;
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s_iLastPERFCycle[0] = cpuRegs.cycle;
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}
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}
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__forceinline void COP0_UpdatePCR1()
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{
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if((cpuRegs.PERF.n.pccr & 0x800F8000) == 0x80008000)
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{
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u32 incr = cpuRegs.cycle-s_iLastPERFCycle[1];
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if( incr == 0 ) incr++;
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cpuRegs.PERF.n.pcr1 += incr;
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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}
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}
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namespace R5900 {
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namespace Interpreter {
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namespace OpcodeImpl {
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namespace COP0 {
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void MFC0() {
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if (!_Rt_) return;
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if (_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getCString() ); }
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void MFC0()
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{
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// Note on _Rd_ Condition 9: CP0.Count should be updated even if _Rt_ is 0.
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if( (_Rd_ != 9) && !_Rt_ ) return;
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if(_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getCString() ); }
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//if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MFC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]);
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switch (_Rd_) {
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switch (_Rd_)
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{
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case 12: cpuRegs.GPR.r[_Rt_].UD[0] = (s64)(cpuRegs.CP0.r[_Rd_] & 0xf0c79c1f); break;
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case 12:
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)(cpuRegs.CP0.r[_Rd_] & 0xf0c79c1f);
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break;
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case 25:
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switch(_Imm_ & 0x3F){
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case 0: cpuRegs.GPR.r[_Rt_].UD[0] = (s64)cpuRegs.PERF.n.pccr; break;
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case 1:
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020) {
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cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
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s_iLastPERFCycle[0] = cpuRegs.cycle;
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}
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cpuRegs.GPR.r[_Rt_].UD[0] = (s64)cpuRegs.PERF.n.pcr0;
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break;
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case 3:
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if((cpuRegs.PERF.n.pccr & 0x800F8000) == 0x80008000) {
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cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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}
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cpuRegs.GPR.r[_Rt_].UD[0] = (s64)cpuRegs.PERF.n.pcr1;
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break;
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switch(_Imm_ & 0x3F)
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{
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case 0: // MFPS [LSB is clear]
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pccr;
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break;
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case 1: // MFPC [LSB is set] - read PCR0
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COP0_UpdatePCR0();
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr0;
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break;
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case 3: // MFPC [LSB is set] - read PCR1
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COP0_UpdatePCR1();
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr1;
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break;
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}
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/*SysPrintf("MFC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);*/
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break;
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break;
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case 24:
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SysPrintf("MFC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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break;
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Console::WriteLn("MFC0 Breakpoint debug Registers code = %x", params cpuRegs.code & 0x3FF);
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break;
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case 9:
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// update
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cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
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{
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u32 incr = cpuRegs.cycle-s_iLastCOP0Cycle;
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if( incr == 0 ) incr++;
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cpuRegs.CP0.n.Count += incr;
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s_iLastCOP0Cycle = cpuRegs.cycle;
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default: cpuRegs.GPR.r[_Rt_].UD[0] = (s64)cpuRegs.CP0.r[_Rd_];
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if( !_Rt_ ) break;
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}
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default:
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cpuRegs.GPR.r[_Rt_].UD[0] = (s64)cpuRegs.CP0.r[_Rd_];
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}
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}
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void MTC0() {
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void MTC0()
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{
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COP0_LOG("%s\n", disR5900Current.getCString());
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//if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MTC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]);
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switch (_Rd_) {
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switch (_Rd_)
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{
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case 25:
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/*if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);*/
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switch(_Imm_ & 0x3F){
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case 0:
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020)
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cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
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if((cpuRegs.PERF.n.pccr & 0x800F8000) == 0x80008000)
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cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
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switch(_Imm_ & 0x3F)
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{
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case 0: // MTPS [LSB is clear]
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// Updates PCRs and sets the PCCR.
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COP0_UpdatePCR0();
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COP0_UpdatePCR1();
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cpuRegs.PERF.n.pccr = cpuRegs.GPR.r[_Rt_].UL[0];
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break;
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case 1: // MTPC [LSB is set] - set PCR0
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cpuRegs.PERF.n.pcr0 = cpuRegs.GPR.r[_Rt_].UL[0];
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s_iLastPERFCycle[0] = cpuRegs.cycle;
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break;
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case 3: // MTPC [LSB is set] - set PCR0
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cpuRegs.PERF.n.pcr1 = cpuRegs.GPR.r[_Rt_].UL[0];
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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break;
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case 1: cpuRegs.PERF.n.pcr0 = cpuRegs.GPR.r[_Rt_].UL[0]; s_iLastPERFCycle[0] = cpuRegs.cycle; break;
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case 3: cpuRegs.PERF.n.pcr1 = cpuRegs.GPR.r[_Rt_].UL[0]; s_iLastPERFCycle[1] = cpuRegs.cycle; break;
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break;
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}
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break;
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break;
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case 24:
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SysPrintf("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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break;
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Console::WriteLn("MTC0 Breakpoint debug Registers code = %x", params cpuRegs.code & 0x3FF);
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break;
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case 12: WriteCP0Status(cpuRegs.GPR.r[_Rt_].UL[0]); break;
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case 9: s_iLastCOP0Cycle = cpuRegs.cycle; cpuRegs.CP0.r[9] = cpuRegs.GPR.r[_Rt_].UL[0]; break;
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default: cpuRegs.CP0.r[_Rd_] = cpuRegs.GPR.r[_Rt_].UL[0]; break;
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case 9:
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s_iLastCOP0Cycle = cpuRegs.cycle;
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cpuRegs.CP0.r[9] = cpuRegs.GPR.r[_Rt_].UL[0];
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break;
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default:
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cpuRegs.CP0.r[_Rd_] = cpuRegs.GPR.r[_Rt_].UL[0];
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break;
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}
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}
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14
pcsx2/COP0.h
14
pcsx2/COP0.h
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@ -19,10 +19,14 @@
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#ifndef __COP0_H__
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#define __COP0_H__
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void WriteCP0Status(u32 value);
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void UpdateCP0Status();
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void WriteTLB(int i);
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void UnmapTLB(int i);
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void MapTLB(int i);
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extern void WriteCP0Status(u32 value);
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extern void UpdateCP0Status();
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extern void WriteTLB(int i);
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extern void UnmapTLB(int i);
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extern void MapTLB(int i);
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extern void COP0_UpdatePCR0();
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extern void COP0_UpdatePCR1();
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#endif /* __COP0_H__ */
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@ -387,19 +387,13 @@ static __forceinline void _cpuTestTIMR()
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static __forceinline void _cpuTestPERF()
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{
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// fixme - The interpreter and recompiler both re-calculate these values
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// whenever they are read, so updating them at regular intervals *should be*
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// merely a common courtesy. But when I set them up to be called less
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// frequently some games would crash. I'd like to figure out why someday. [Air]
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// Perfs are updated when read by games (COP0's MFC0/MTC0 instructions), so we need
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// only update them at semi-regular intervals to keep cpuRegs.cycle from wrapping
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// around twice on us btween updates. Hence this function is called from the cpu's
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// Counters update.
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020) {
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cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
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s_iLastPERFCycle[0] = cpuRegs.cycle;
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}
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if((cpuRegs.PERF.n.pccr & 0x800F8000) == 0x80008000) {
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cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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}
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COP0_UpdatePCR0();
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COP0_UpdatePCR1();
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}
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// Checks the COP0.Status for exception enablings.
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@ -128,16 +128,21 @@ void recMFC0( void )
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{
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int mmreg;
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if ( ! _Rt_ ) return;
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if( _Rd_ == 9 ) {
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if( _Rd_ == 9 )
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{
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// This case needs to be handled even if the write-back is ignored (_Rt_ == 0 )
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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MOV32RtoR(EAX,ECX);
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MOV32RtoR(EAX, ECX);
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SUB32MtoR(EAX, (uptr)&s_iLastCOP0Cycle);
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u8* skipInc = JNZ8( 0 );
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INC32R(EAX);
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x86SetJ8( skipInc );
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ADD32RtoM((uptr)&cpuRegs.CP0.n.Count, EAX);
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MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
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MOV32MtoR( EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ] );
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if( !_Rt_ ) return;
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_deleteEEreg(_Rt_, 0);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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@ -148,34 +153,37 @@ void recMFC0( void )
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else EEINST_RESETHASLIVE1(_Rt_);
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return;
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}
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if( _Rd_ == 25 ) {
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_deleteEEreg(_Rt_, 0);
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switch(_Imm_ & 0x3F){
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if ( !_Rt_ ) return;
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if( _Rd_ == 25 )
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{
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switch(_Imm_ & 0x3F)
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{
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case 0:
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
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break;
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break;
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case 1:
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// check if needs to be incremented
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MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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/*MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pcr0);
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AND32ItoR(ECX, 0x800003E0);
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CMP32ItoR(ECX, 0x80000020);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EDX, (uptr)&cpuRegs.cycle);
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SUB32MtoR(EAX, (uptr)&s_iLastPERFCycle[0]);
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ADD32RtoR(EAX, EDX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], EDX);
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MOV32RtoM((uptr)&cpuRegs.PERF.n.pcr0, EAX);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[0]);*/
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CALLFunc( (uptr)COP0_UpdatePCR0 );
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break;
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case 3:
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// check if needs to be incremented
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MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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/*MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pcr1);
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AND32ItoR(ECX, 0x800F8000);
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@ -188,12 +196,13 @@ void recMFC0( void )
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], EDX);
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MOV32RtoM((uptr)&cpuRegs.PERF.n.pcr1, EAX);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[0]);*/
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CALLFunc( (uptr)COP0_UpdatePCR1 );
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break;
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}
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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_deleteEEreg(_Rt_, 0);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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CDQ();
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@ -201,10 +210,6 @@ void recMFC0( void )
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}
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else EEINST_RESETHASLIVE1(_Rt_);
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#ifdef PCSX2_DEVBUILD
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COP0_LOG("MFC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
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#endif
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return;
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}
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else if( _Rd_ == 24){
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@ -283,93 +288,100 @@ void updatePCCR()
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void recMTC0()
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{
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if( GPR_IS_CONST1(_Rt_) ) {
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switch (_Rd_) {
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if( GPR_IS_CONST1(_Rt_) )
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{
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switch (_Rd_)
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{
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case 12:
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iFlushCall(FLUSH_NODESTROY);
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//_flushCachedRegs(); //NOTE: necessary?
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_callFunctionArg1((uptr)WriteCP0Status, MEM_CONSTTAG, g_cpuConstRegs[_Rt_].UL[0]);
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break;
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break;
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case 9:
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
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MOV32ItoM((uptr)&cpuRegs.CP0.r[9], g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 25:
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COP0_LOG("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
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switch(_Imm_ & 0x3F){
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case 0:
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updatePCCR();
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MOV32ItoM((uptr)&cpuRegs.PERF.n.pccr, g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 25:
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switch(_Imm_ & 0x3F)
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{
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case 0:
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CALLFunc( (uptr)COP0_UpdatePCR0 );
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CALLFunc( (uptr)COP0_UpdatePCR1 );
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MOV32ItoM((uptr)&cpuRegs.PERF.n.pccr, g_cpuConstRegs[_Rt_].UL[0]);
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break;
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// update the cycles
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
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break;
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case 1:
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MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
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MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr0, g_cpuConstRegs[_Rt_].UL[0]);
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], EAX);
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break;
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break;
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case 3:
|
||||
MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
|
||||
MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr1, g_cpuConstRegs[_Rt_].UL[0]);
|
||||
MOV32RtoM((uptr)&s_iLastPERFCycle[1], EAX);
|
||||
break;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
break;
|
||||
|
||||
case 24:
|
||||
COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
|
||||
break;
|
||||
break;
|
||||
|
||||
default:
|
||||
MOV32ItoM((uptr)&cpuRegs.CP0.r[_Rd_], g_cpuConstRegs[_Rt_].UL[0]);
|
||||
break;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else {
|
||||
switch (_Rd_) {
|
||||
else
|
||||
{
|
||||
switch (_Rd_)
|
||||
{
|
||||
case 12:
|
||||
iFlushCall(FLUSH_NODESTROY);
|
||||
//_flushCachedRegs(); //NOTE: necessary?
|
||||
_callFunctionArg1((uptr)WriteCP0Status, MEM_GPRTAG|_Rt_, 0);
|
||||
break;
|
||||
break;
|
||||
|
||||
case 9:
|
||||
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||
_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_);
|
||||
MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
|
||||
break;
|
||||
case 25:
|
||||
COP0_LOG("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
|
||||
cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
|
||||
switch(_Imm_ & 0x3F){
|
||||
case 0:
|
||||
updatePCCR();
|
||||
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
|
||||
break;
|
||||
|
||||
case 25:
|
||||
switch(_Imm_ & 0x3F)
|
||||
{
|
||||
case 0:
|
||||
CALLFunc( (uptr)COP0_UpdatePCR0 );
|
||||
CALLFunc( (uptr)COP0_UpdatePCR1 );
|
||||
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
|
||||
break;
|
||||
|
||||
// update the cycles
|
||||
MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
|
||||
MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
|
||||
break;
|
||||
case 1:
|
||||
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_);
|
||||
MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
|
||||
break;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_);
|
||||
MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
|
||||
break;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
break;
|
||||
|
||||
case 24:
|
||||
COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
|
||||
break;
|
||||
break;
|
||||
|
||||
default:
|
||||
_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[_Rd_], _Rt_);
|
||||
break;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue