mirror of https://github.com/PCSX2/pcsx2.git
EE: remove most of MMX allocator code
This commit is contained in:
Gregory Hainaut
parent
278411898a
commit
0f81482ed1
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@ -33,7 +33,7 @@ u16 g_xmmAllocCounter = 0;
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EEINST* g_pCurInstInfo = NULL;
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// used to make sure regs don't get changed while in recompiler
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// use FreezeMMXRegs, FreezeXMMRegs
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// use FreezeXMMRegs
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u32 g_recWriteback = 0;
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_xmmregs xmmregs[iREGCNT_XMM], s_saveXMMregs[iREGCNT_XMM];
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@ -268,51 +268,6 @@ int _allocCheckFPUtoXMM(EEINST* pinst, int fpureg, int mode);
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// allocates only if later insts use this register
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int _allocCheckGPRtoX86(EEINST* pinst, int gprreg, int mode);
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////////////////////////////////////////////////////////////////////////////////
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// MMX (64-bit) Register Allocation Tools
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// max is 0x7f, when 0x80 is set, need to flush reg
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//#define MMX_GET_CACHE(ptr, index) ((u8*)ptr)[index]
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//#define MMX_SET_CACHE(ptr, ind3, ind2, ind1, ind0) ((u32*)ptr)[0] = (ind3<<24)|(ind2<<16)|(ind1<<8)|ind0;
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#define MMX_GPR 0
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#define MMX_HI XMMGPR_HI
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#define MMX_LO XMMGPR_LO
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#define MMX_FPUACC 34
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#define MMX_FPU 64
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#define MMX_COP0 96
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#define MMX_TEMP 0x7f
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static __fi bool MMX_IS32BITS(s32 x)
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{
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return (((x >= MMX_FPU) && (x < MMX_COP0 + 32)) || (x == MMX_FPUACC));
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}
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static __fi bool MMX_ISGPR(s32 x)
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{
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return ((x >= MMX_GPR) && (x < MMX_GPR + 34));
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}
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static __fi bool MMX_ISGPR(u32 x)
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{
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return (x < MMX_GPR + 34);
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}
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struct _mmxregs {
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u8 inuse;
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u8 reg; // value of 0 - not used
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u8 mode;
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u8 needed;
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u16 counter;
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};
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void _initMMXregs();
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u8 _hasFreeMMXreg();
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int _getNumMMXwrite();
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extern _mmxregs mmxregs[iREGCNT_MMX], s_saveMMXregs[iREGCNT_MMX];
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// extern void iDumpRegisters(u32 startpc, u32 temp);
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//////////////////////////////////////////////////////////////////////////
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// iFlushCall / _psxFlushCall Parameters
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@ -331,8 +286,6 @@ extern _mmxregs mmxregs[iREGCNT_MMX], s_saveMMXregs[iREGCNT_MMX];
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#define FLUSH_CACHED_REGS 0x001
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#define FLUSH_FLUSH_XMM 0x002
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#define FLUSH_FREE_XMM 0x004 // both flushes and frees
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#define FLUSH_FLUSH_MMX 0x008
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#define FLUSH_FREE_MMX 0x010 // both flushes and frees
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#define FLUSH_FLUSH_ALLX86 0x020 // flush x86
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#define FLUSH_FREE_TEMPX86 0x040 // flush and free temporary x86 regs
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#define FLUSH_FREE_ALLX86 0x080 // free all x86 regs
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@ -346,9 +299,9 @@ extern _mmxregs mmxregs[iREGCNT_MMX], s_saveMMXregs[iREGCNT_MMX];
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#define FLUSH_INTERPRETER 0xfff
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#define FLUSH_FULLVTLB FLUSH_NOCONST
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// no freeing, used when callee won't destroy mmx/xmm regs
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#define FLUSH_NODESTROY (FLUSH_CACHED_REGS|FLUSH_FLUSH_XMM|FLUSH_FLUSH_MMX|FLUSH_FLUSH_ALLX86)
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// no freeing, used when callee won't destroy xmm regs
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#define FLUSH_NODESTROY (FLUSH_CACHED_REGS|FLUSH_FLUSH_XMM|FLUSH_FLUSH_ALLX86)
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// used when regs aren't going to be changed be callee
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#define FLUSH_NOCONST (FLUSH_FREE_XMM|FLUSH_FREE_MMX|FLUSH_FREE_TEMPX86)
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#define FLUSH_NOCONST (FLUSH_FREE_XMM|FLUSH_FREE_TEMPX86)
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#endif
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@ -28,8 +28,6 @@ using namespace x86Emitter;
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// landmass of shared code. (air)
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extern u32 g_psxConstRegs[32];
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static u16 g_mmxAllocCounter = 0;
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// X86 caching
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static int g_x86checknext;
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@ -469,23 +467,7 @@ void _freeX86regs()
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_freeX86reg(i);
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}
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// MMX Caching
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_mmxregs mmxregs[8], s_saveMMXregs[8];
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static int s_mmxchecknext = 0;
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void _initMMXregs()
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{
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memzero(mmxregs);
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g_mmxAllocCounter = 0;
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s_mmxchecknext = 0;
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}
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int _getNumMMXwrite()
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{
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uint num = 0, i;
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return num;
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}
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// Misc
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void _signExtendSFtoM(uptr mem)
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{
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@ -231,11 +231,6 @@ int _flushXMMunused()
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return 0;
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}
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int _flushMMXunused()
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{
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return 0;
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}
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int _flushUnusedConstReg()
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{
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int i;
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@ -906,8 +901,6 @@ void SaveBranchState()
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s_saveFlushedConstReg = g_cpuFlushedConstReg;
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s_psaveInstInfo = g_pCurInstInfo;
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// save all mmx regs
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memcpy(s_saveMMXregs, mmxregs, sizeof(mmxregs));
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memcpy(s_saveXMMregs, xmmregs, sizeof(xmmregs));
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}
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@ -920,8 +913,6 @@ void LoadBranchState()
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g_cpuFlushedConstReg = s_saveFlushedConstReg;
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g_pCurInstInfo = s_psaveInstInfo;
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// restore all mmx regs
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memcpy(mmxregs, s_saveMMXregs, sizeof(mmxregs));
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memcpy(xmmregs, s_saveXMMregs, sizeof(xmmregs));
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}
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@ -1267,15 +1258,6 @@ void recompileNextInstruction(int delayslot)
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g_pCurInstInfo++;
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for(i = 0; i < iREGCNT_MMX; ++i) {
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if( mmxregs[i].inuse ) {
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pxAssert( MMX_ISGPR(mmxregs[i].reg) );
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count = _recIsRegWritten(g_pCurInstInfo, (s_nEndBlock-pc)/4 + 1, XMMTYPE_GPRREG, mmxregs[i].reg-MMX_GPR);
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if( count > 0 ) mmxregs[i].counter = 1000-count;
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else mmxregs[i].counter = 0;
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}
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}
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for(i = 0; i < iREGCNT_XMM; ++i) {
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if( xmmregs[i].inuse ) {
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count = _recIsRegWritten(g_pCurInstInfo, (s_nEndBlock-pc)/4 + 1, xmmregs[i].type, xmmregs[i].reg);
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@ -1332,7 +1314,7 @@ void recompileNextInstruction(int delayslot)
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if( s_bFlushReg ) {
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//if( !_flushUnusedConstReg() ) {
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int flushed = 0;
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if( _getNumMMXwrite() > 3 ) flushed = _flushMMXunused();
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if( false ) flushed = 0; // old mmx path. I don't understand why flushed isn't set in the line below
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if( !flushed && _getNumXMMwrite() > 2 ) _flushXMMunused();
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s_bFlushReg = !flushed;
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// }
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@ -1650,7 +1632,6 @@ static void __fastcall recRecompile( const u32 startpc )
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_initX86regs();
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_initXMMregs();
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_initMMXregs();
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if( EmuConfig.Cpu.Recompiler.PreBlockCheckEE )
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{
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@ -75,8 +75,9 @@ int eeProcessHILO(int reg, int mode, int mmx)
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return -1;
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}
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#define PROCESS_EE_SETMODES(mmreg) ((mmxregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITES:0)
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#define PROCESS_EE_SETMODET(mmreg) ((mmxregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITET:0)
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// Strangely this code is used on NOT-MMX path ...
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#define PROCESS_EE_SETMODES(mmreg) (/*(mmxregs[mmreg].mode&MODE_WRITE)*/ false ?PROCESS_EE_MODEWRITES:0)
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#define PROCESS_EE_SETMODET(mmreg) (/*(mmxregs[mmreg].mode&MODE_WRITE)*/ false ?PROCESS_EE_MODEWRITET:0)
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// ignores XMMINFO_READS, XMMINFO_READT, and XMMINFO_READD_LO from xmminfo
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// core of reg caching
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@ -2545,7 +2545,6 @@ void SuperVUCleanupProgram(u32 startpc, int vuindex)
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// Could clear allocation info to prevent possibly bad data being used in other parts of pcsx2;
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// not doing this because it's slow and not needed (rama)
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// _initXMMregs();
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// _initMMXregs();
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// _initX86regs();
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}
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