mirror of https://github.com/PCSX2/pcsx2.git
- Nneeve fixed the Tri-Ace gamefix so Gradius5 doesn't crash with it enabled anymore.
- Moved one global variable for the VU interpreters, which surprisingly speeds up Star Ocean 3 for me. - Set Flush to Zero for FPU and VU back to on. Let's see how long it lasts this time :p - Removed the FFX hack from pcsx2! It's still toggled in the GS plugins, the correct behaviour is having it always on. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@848 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
parent
1df68eca73
commit
0e61bd6b35
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@ -81,8 +81,8 @@ extern SessionOverrideFlags g_Session;
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#define DEFAULT_eeOptions 0x01
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#define DEFAULT_vuOptions 0x01
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//------------ DEFAULT sseMXCSR VALUES!!! ---------------
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#define DEFAULT_sseMXCSR 0x7fc0 //FPU rounding, DaZ, "chop" - Note: Dont enable FtZ by default, it breaks games! E.g. Enthusia (Refraction)
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#define DEFAULT_sseVUMXCSR 0x7fc0 //VU rounding, DaZ, "chop"
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#define DEFAULT_sseMXCSR 0xffc0 //FPU rounding > DaZ, FtZ, "chop"
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#define DEFAULT_sseVUMXCSR 0xffc0 //VU rounding > DaZ, FtZ, "chop"
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#define CHECK_FRAMELIMIT (Config.Options&PCSX2_FRAMELIMIT_MASK)
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@ -571,7 +571,6 @@ int loadElfFile(const char *filename)
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}
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#include "VU.h"
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extern int g_FFXHack;
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extern int path3hack;
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int g_VUGameFixes = 0;
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@ -580,7 +579,6 @@ void LoadGameSpecificSettings()
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{
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// default
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g_VUGameFixes = 0;
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g_FFXHack = 0;
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switch(ElfCRC) {
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case 0xb99379b7: // erementar gerad (discolored chars)
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@ -589,33 +587,6 @@ void LoadGameSpecificSettings()
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case 0xa08c4057: //Sprint Cars (SLUS)
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case 0x8b0725d5: //Flinstones Bedrock Racing (SLES)
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path3hack = 1; // We can move this to patch files right now
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break;
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case 0xb4414ea1: // ffx(rus)
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case 0xee97db5b: // ffx(rus)
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case 0xaec495cc: // ffx(rus)
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case 0x6a4efe60: // ffx(j)
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case 0xA39517AB: // ffx(e)
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case 0xBB3D833A: // ffx(u)
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case 0x941bb7d9: // ffx(g)
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case 0xD9FC6310: // ffx int(j)
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case 0xa39517ae: // ffx(f)
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case 0xa39517a9: // ffx(i)
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case 0x658597e2: // ffx int
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case 0x941BB7DE: // ffx(s)
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case 0x3866CA7E: // ffx(asia)
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case 0x48FE0C71: // ffx2 (u)
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case 0x9aac530d: // ffx2 (g)
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case 0x9AAC5309: // ffx2 (e)
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case 0x8A6D7F14: // ffx2 (j)
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case 0x9AAC530B: // ffx2 (i)
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case 0x9AAC530A: // ffx2 (f)
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case 0x9aac530c: // ffx2 (f)
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case 0xe1fd9a2d: // ffx2 last mission (?)
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case 0x93f9b89a: // ffx2 demo (g)
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case 0x304C115C: // harvest moon - awl
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case 0xF0A6D880: // harvest moon - sth
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g_FFXHack = 1;
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break;
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}
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}
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@ -41,8 +41,6 @@ using namespace R5900;
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static bool m_gsOpened = false;
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int g_FFXHack=0;
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#ifdef PCSX2_DEVBUILD
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// GS Playback
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@ -327,7 +327,7 @@ __forceinline u32 mtgsThreadObject::_gifTransferDummy( GIF_PATH pathidx, const u
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}
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else if(path.tag.nloop == 0)
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{
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if(pathidx == 0 && g_FFXHack)
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if(pathidx == 0)
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continue;
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eop = true;
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@ -653,7 +653,8 @@ int AddPatch(int Mode, int Place, int Address, int Size, u64 data)
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void patchFunc_ffxhack( char * cmd, char * param )
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{
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g_FFXHack = 1;
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//Keeping this as a dummy a while :p
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//g_FFXHack = 1;
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}
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void patchFunc_xkickdelay( char * cmd, char * param )
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@ -110,7 +110,6 @@ int AddPatch(int Mode, int Place, int Address, int Size, u64 data);
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extern void SetFastMemory(int); // iR5900LoadStore.c
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extern int path3hack;
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extern int g_FFXHack;
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//extern int g_VUGameFixes;
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extern int g_ZeroGSOptions;
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extern u32 g_sseMXCSR;
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@ -316,7 +316,6 @@ void _vuAddLowerStalls(VURegs * VU, _VURegsNum *VUregsn) {
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/* VU Upper instructions */
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/******************************/
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#ifndef INT_VUDOUBLEHACK
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static u32 d;
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float vuDouble(u32 f)
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{
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switch(f & 0x7f800000){
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@ -324,10 +323,13 @@ float vuDouble(u32 f)
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f &= 0x80000000;
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return *(float*)&f;
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break;
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case 0x7f800000:
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case 0x7f800000:
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{
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u32 d;
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d = (f & 0x80000000)|0x7f7fffff;
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return *(float*)&d;
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break;
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}
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default:
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return *(float*)&f;
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break;
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@ -2718,7 +2720,8 @@ void _vuRegsFSSET(VURegs * VU, _VURegsNum *VUregsn) {
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VUregsn->VFread0 = 0;
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VUregsn->VFread1 = 0;
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VUregsn->VIwrite = 1 << REG_STATUS_FLAG;
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VUregsn->VIread = 0;//1 << REG_STATUS_FLAG; this kills speed
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//VUregsn->VIread = 0; // 1 << REG_STATUS_FLAG; this kills speed. Todo: Orly? (rama)
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VUregsn->VIread = 1 << REG_STATUS_FLAG;
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}
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void _vuRegsFMAND(VURegs * VU, _VURegsNum *VUregsn) {
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@ -333,12 +333,23 @@ void recUpdateFlags(VURegs * VU, int reg, int info)
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static PCSX2_ALIGNED16(u32 VU_addsuband[2][4]);
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static PCSX2_ALIGNED16(u32 VU_addsub_reg[2][4]);
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static u32 tempECX;
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void VU_ADD_SUB(u32 regd, u32 regt, int is_sub, int info)
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{
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u8 *localptr[4][8];
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int temp1 = _allocX86reg(ECX, X86TYPE_TEMP, 0, 0); //receives regd
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MOV32RtoM((uptr)&tempECX, ECX);
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int temp1 = ECX; //receives regd
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int temp2 = ALLOCTEMPX86(0);
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if (temp2 == ECX)
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{
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temp2 = ALLOCTEMPX86(0);
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_freeX86reg(ECX);
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}
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SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[0][0], regd);
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SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[1][0], regt);
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SSE_MOVAPS_M128_to_XMM(regt, (uptr)&VU_addsub_reg[1][0]);
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_freeX86reg(temp1);
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_freeX86reg(temp2);
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}
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void VU_ADD_SUB_SSE4(u32 regd, u32 regt, int is_sub, int info)
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{
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u8 *localptr[4][8];
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int temp1 = _allocX86reg(ECX, X86TYPE_TEMP, 0, 0); //receives regd
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int temp2 = ALLOCTEMPX86(0);
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SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[0][0], regd);
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SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[1][0], regt);
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SSE2_PSLLD_I8_to_XMM(regd, 1);
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SSE2_PSLLD_I8_to_XMM(regt, 1);
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SSE2_PSRLD_I8_to_XMM(regd, 24);
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SSE2_PSRLD_I8_to_XMM(regt, 24);
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SSE2_PSUBD_XMM_to_XMM(regd, regt);
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#define PERFORM_SSE4(i) \
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\
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SSE_PEXTRW_XMM_to_R32(temp1, regd, i*2); \
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MOVSX32R16toR(temp1, temp1); \
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CMP32ItoR(temp1, 25);\
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localptr[i][0] = JGE8(0);\
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CMP32ItoR(temp1, 0);\
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localptr[i][1] = JG8(0);\
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localptr[i][2] = JE8(0);\
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CMP32ItoR(temp1, -25);\
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localptr[i][3] = JLE8(0);\
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\
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NEG32R(temp1); \
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DEC32R(temp1);\
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MOV32ItoR(temp2, 0xffffffff); \
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SHL32CLtoR(temp2); \
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SSE4_PINSRD_R32_to_XMM(regd, temp2, i); \
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localptr[i][4] = JMP8(0);\
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\
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x86SetJ8(localptr[i][0]);\
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MOV32ItoR(temp2, 0xffffffff); \
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SSE4_PINSRD_R32_to_XMM(regd, temp2, i); \
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SHL32ItoR(temp2, 31); \
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SSE4_PINSRD_R32_to_XMM(regt, temp2, i); \
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localptr[i][5] = JMP8(0);\
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\
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x86SetJ8(localptr[i][1]);\
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DEC32R(temp1);\
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MOV32ItoR(temp2, 0xffffffff);\
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SSE4_PINSRD_R32_to_XMM(regd, temp2, i); \
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SHL32CLtoR(temp2); \
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SSE4_PINSRD_R32_to_XMM(regt, temp2, i); \
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localptr[i][6] = JMP8(0);\
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\
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x86SetJ8(localptr[i][3]);\
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MOV32ItoR(temp2, 0x80000000); \
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SSE4_PINSRD_R32_to_XMM(regd, temp2, i); \
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localptr[i][7] = JMP8(0);\
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\
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x86SetJ8(localptr[i][2]);\
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\
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x86SetJ8(localptr[i][4]);\
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x86SetJ8(localptr[i][5]);\
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x86SetJ8(localptr[i][6]);\
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x86SetJ8(localptr[i][7]);
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SSE2_PCMPEQB_XMM_to_XMM(regt, regt);
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PERFORM_SSE4(0);
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PERFORM_SSE4(1);
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PERFORM_SSE4(2);
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PERFORM_SSE4(3);
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#undef PERFORM_SSE4
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SSE_ANDPS_M128_to_XMM(regd, (uptr)&VU_addsub_reg[0][0]); //regd contains mask
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SSE_ANDPS_M128_to_XMM(regt, (uptr)&VU_addsub_reg[1][0]); //regt contains mask
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if (is_sub) SSE_SUBPS_XMM_to_XMM(regd, regt);
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else SSE_ADDPS_XMM_to_XMM(regd, regt);
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SSE_MOVAPS_M128_to_XMM(regt, (uptr)&VU_addsub_reg[1][0]);
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_freeX86reg(temp1);
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_freeX86reg(temp2);
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MOV32MtoR(ECX, (uptr)&tempECX);
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}
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void VU_ADD_SUB_SS(u32 regd, u32 regt, int is_sub, int is_mem, int info)
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{
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u8 *localptr[8];
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u32 addrt = regt; //for case is_mem
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int temp1 = _allocX86reg(ECX, X86TYPE_TEMP, 0, 0); //receives regd //_allocX86reg(ECX, X86TYPE_TEMP, 0, ((info&PROCESS_VU_SUPER)?0:MODE_NOFRAME)|mode);
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MOV32RtoM((uptr)&tempECX, ECX);
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int temp1 = ECX; //receives regd
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int temp2 = ALLOCTEMPX86(0);
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if (temp2 == ECX)
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{
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temp2 = ALLOCTEMPX86(0);
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_freeX86reg(ECX);
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}
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SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[0][0], regd);
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if (!is_mem) SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[1][0], regt);
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@ -617,167 +556,44 @@ void VU_ADD_SUB_SS(u32 regd, u32 regt, int is_sub, int is_mem, int info)
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SSE_MOVAPS_M128_to_XMM(regt, (uptr)&VU_addsub_reg[1][0]);
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}
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_freeX86reg(temp1);
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_freeX86reg(temp2);
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}
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void VU_ADD_SUB_SS_SSE4(u32 regd, u32 regt, int is_sub, int is_mem, int info)
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{
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u8 *localptr[8];
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u32 addrt = regt; //for case is_mem
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int temp1 = _allocX86reg(ECX, X86TYPE_TEMP, 0, 0); //receives regd //_allocX86reg(ECX, X86TYPE_TEMP, 0, ((info&PROCESS_VU_SUPER)?0:MODE_NOFRAME)|mode);
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int temp2 = ALLOCTEMPX86(0);
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SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[0][0], regd);
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if (!is_mem) SSE_MOVAPS_XMM_to_M128((uptr)&VU_addsub_reg[1][0], regt);
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SSE2_MOVD_XMM_to_R(temp1, regd);
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SHR32ItoR(temp1, 23);
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if (is_mem) {
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MOV32MtoR(temp2, addrt);
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MOV32RtoM((uptr)&VU_addsub_reg[1][0], temp2);
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SHR32ItoR(temp2, 23);
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}
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else {
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SSE2_MOVD_XMM_to_R(temp2, regt);
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SHR32ItoR(temp2, 23);
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}
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AND32ItoR(temp1, 0xff);
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AND32ItoR(temp2, 0xff);
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SUB32RtoR(temp1, temp2); //temp1 = exponent difference
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CMP32ItoR(temp1, 25);
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localptr[0] = JGE8(0);
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CMP32ItoR(temp1, 0);
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localptr[1] = JG8(0);
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localptr[2] = JE8(0);
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CMP32ItoR(temp1, -25);
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localptr[3] = JLE8(0);
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NEG32R(temp1);
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DEC32R(temp1);
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MOV32ItoR(temp2, 0xffffffff);
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SHL32CLtoR(temp2);
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SSE2_PCMPEQB_XMM_to_XMM(regd, regd);
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SSE4_PINSRD_R32_to_XMM(regd, temp2, 0);
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if (!is_mem)
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SSE2_PCMPEQB_XMM_to_XMM(regt, regt);
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localptr[4] = JMP8(0);
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x86SetJ8(localptr[0]);
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MOV32ItoR(temp2, 0x80000000);
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if (is_mem)
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AND32RtoM((uptr)&VU_addsub_reg[1][0], temp2);
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else {
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SSE2_PCMPEQB_XMM_to_XMM(regt, regt);
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SSE4_PINSRD_R32_to_XMM(regt, temp2, 0);
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}
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SSE2_PCMPEQB_XMM_to_XMM(regd, regd);
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localptr[5] = JMP8(0);
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x86SetJ8(localptr[1]);
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DEC32R(temp1);
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MOV32ItoR(temp2, 0xffffffff);
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SHL32CLtoR(temp2);
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if (is_mem)
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AND32RtoM((uptr)&VU_addsub_reg[1][0], temp2);
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else {
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SSE2_PCMPEQB_XMM_to_XMM(regt, regt);
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SSE4_PINSRD_R32_to_XMM(regt, temp2, 0);
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}
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SSE2_PCMPEQB_XMM_to_XMM(regd, regd);
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localptr[6] = JMP8(0);
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x86SetJ8(localptr[3]);
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MOV32ItoR(temp2, 0x80000000);
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SSE2_PCMPEQB_XMM_to_XMM(regd, regd);
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SSE4_PINSRD_R32_to_XMM(regd, temp2, 0);
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if (!is_mem)
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SSE2_PCMPEQB_XMM_to_XMM(regt, regt);
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localptr[7] = JMP8(0);
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x86SetJ8(localptr[2]);
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x86SetJ8(localptr[4]);
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x86SetJ8(localptr[5]);
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x86SetJ8(localptr[6]);
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x86SetJ8(localptr[7]);
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if (is_mem)
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{
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SSE_ANDPS_M128_to_XMM(regd, (uptr)&VU_addsub_reg[0][0]); //regd contains mask
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if (is_sub) SSE_SUBSS_M32_to_XMM(regd, (uptr)&VU_addsub_reg[1][0]);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&VU_addsub_reg[1][0]);
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}
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else
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{
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SSE_ANDPS_M128_to_XMM(regd, (uptr)&VU_addsub_reg[0][0]); //regd contains mask
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SSE_ANDPS_M128_to_XMM(regt, (uptr)&VU_addsub_reg[1][0]); //regt contains mask
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if (is_sub) SSE_SUBSS_XMM_to_XMM(regd, regt);
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else SSE_ADDSS_XMM_to_XMM(regd, regt);
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SSE_MOVAPS_M128_to_XMM(regt, (uptr)&VU_addsub_reg[1][0]);
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||||
}
|
||||
|
||||
_freeX86reg(temp1);
|
||||
_freeX86reg(temp2);
|
||||
MOV32MtoR(ECX, (uptr)&tempECX);
|
||||
}
|
||||
|
||||
void SSE_ADDPS_XMM_to_XMM_custom(int info, int regd, int regt) {
|
||||
if (CHECK_VUADDSUBHACK) {
|
||||
if ( cpucaps.hasStreamingSIMD4Extensions )
|
||||
VU_ADD_SUB_SSE4(regd, regt, 0, info);
|
||||
else
|
||||
VU_ADD_SUB(regd, regt, 0, info);
|
||||
VU_ADD_SUB(regd, regt, 0, info);
|
||||
}
|
||||
else SSE_ADDPS_XMM_to_XMM(regd, regt);
|
||||
}
|
||||
void SSE_SUBPS_XMM_to_XMM_custom(int info, int regd, int regt) {
|
||||
if (CHECK_VUADDSUBHACK) {
|
||||
if ( cpucaps.hasStreamingSIMD4Extensions )
|
||||
VU_ADD_SUB_SSE4(regd, regt, 1, info);
|
||||
else
|
||||
VU_ADD_SUB(regd, regt, 1, info);
|
||||
VU_ADD_SUB(regd, regt, 1, info);
|
||||
}
|
||||
else SSE_SUBPS_XMM_to_XMM(regd, regt);
|
||||
}
|
||||
void SSE_ADDSS_XMM_to_XMM_custom(int info, int regd, int regt) {
|
||||
if (CHECK_VUADDSUBHACK) {
|
||||
if ( cpucaps.hasStreamingSIMD4Extensions )
|
||||
VU_ADD_SUB_SS_SSE4(regd, regt, 0, 0, info);
|
||||
else
|
||||
VU_ADD_SUB_SS(regd, regt, 0, 0, info);
|
||||
VU_ADD_SUB_SS(regd, regt, 0, 0, info);
|
||||
}
|
||||
else SSE_ADDSS_XMM_to_XMM(regd, regt);
|
||||
}
|
||||
void SSE_SUBSS_XMM_to_XMM_custom(int info, int regd, int regt) {
|
||||
if (CHECK_VUADDSUBHACK) {
|
||||
if ( cpucaps.hasStreamingSIMD4Extensions )
|
||||
VU_ADD_SUB_SS_SSE4(regd, regt, 1, 0, info);
|
||||
else
|
||||
VU_ADD_SUB_SS(regd, regt, 1, 0, info);
|
||||
VU_ADD_SUB_SS(regd, regt, 1, 0, info);
|
||||
}
|
||||
else SSE_SUBSS_XMM_to_XMM(regd, regt);
|
||||
}
|
||||
void SSE_ADDSS_M32_to_XMM_custom(int info, int regd, int regt) {
|
||||
if (CHECK_VUADDSUBHACK) {
|
||||
if ( cpucaps.hasStreamingSIMD4Extensions )
|
||||
VU_ADD_SUB_SS_SSE4(regd, regt, 0, 1, info);
|
||||
else
|
||||
VU_ADD_SUB_SS(regd, regt, 0, 1, info);
|
||||
VU_ADD_SUB_SS(regd, regt, 0, 1, info);
|
||||
}
|
||||
else SSE_ADDSS_M32_to_XMM(regd, regt);
|
||||
}
|
||||
void SSE_SUBSS_M32_to_XMM_custom(int info, int regd, int regt) {
|
||||
if (CHECK_VUADDSUBHACK) {
|
||||
if ( cpucaps.hasStreamingSIMD4Extensions )
|
||||
VU_ADD_SUB_SS_SSE4(regd, regt, 1, 1, info);
|
||||
else
|
||||
VU_ADD_SUB_SS(regd, regt, 1, 1, info);
|
||||
VU_ADD_SUB_SS(regd, regt, 1, 1, info);
|
||||
}
|
||||
else SSE_SUBSS_M32_to_XMM(regd, regt);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue