mirror of https://github.com/PCSX2/pcsx2.git
nneeve fixed min/max FPU opcodes to be more precise when running in "Full" clamp mode.
he also cleaned up some other stuff in iFPUd.cpp git-svn-id: http://pcsx2.googlecode.com/svn/trunk@744 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
022fdf1bf3
commit
0bcb9cc0e3
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@ -26,16 +26,18 @@
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/* Version of the FPU that emulates an exponent of 0xff and overflow/underflow flags */
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/* Can be made faster by not converting stuff back and forth between instructions. */
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//set overflow flag (set only if FPU_RESULT is 1)
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#define FPU_FLAGS_OVERFLOW 1
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//set underflow flag (set only if FPU_RESULT is 1)
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#define FPU_FLAGS_UNDERFLOW 1
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//if 1, result is not clamped (MORE correct,
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//if 1, result is not clamped (Gives correct results as in PS2,
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//but can cause problems due to insuffecient clamping levels in the VUs)
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#define FPU_RESULT 1
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//also impacts other aspects of DIV/R/SQRT correctness
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//set I&D flags. also impacts other aspects of DIV/R/SQRT correctness
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#define FPU_FLAGS_ID 1
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//------------------------------------------------------------------
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@ -128,268 +130,6 @@ static u32 PCSX2_ALIGNED16(s_pos[4]) = { 0x7fffffff, 0xffffffff, 0xffffffff, 0xf
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// *FPU Opcodes!*
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// CFC1 / CTC1
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//------------------------------------------------------------------
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void recCFC1(void)
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{
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if ( !_Rt_ || ( (_Fs_ != 0) && (_Fs_ != 31) ) ) return;
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_eeOnWriteReg(_Rt_, 1);
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MOV32MtoR( EAX, (uptr)&fpuRegs.fprc[ _Fs_ ] );
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_deleteEEreg(_Rt_, 0);
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if (_Fs_ == 31)
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{
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AND32ItoR(EAX, 0x0083c078); //remove always-zero bits
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OR32ItoR(EAX, 0x01000001); //set always-one bits
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}
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if(EEINST_ISLIVE1(_Rt_))
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{
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CDQ( );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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}
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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}
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}
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void recCTC1( void )
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{
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if ( _Fs_ != 31 ) return;
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if ( GPR_IS_CONST1(_Rt_) )
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{
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MOV32ItoM((uptr)&fpuRegs.fprc[ _Fs_ ], g_cpuConstRegs[_Rt_].UL[0]);
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}
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else
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{
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int mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( mmreg >= 0 )
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{
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SSEX_MOVD_XMM_to_M32((uptr)&fpuRegs.fprc[ _Fs_ ], mmreg);
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}
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else
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{
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mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ);
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if ( mmreg >= 0 )
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{
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MOVDMMXtoM((uptr)&fpuRegs.fprc[ _Fs_ ], mmreg);
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SetMMXstate();
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}
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else
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{
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_deleteGPRtoXMMreg(_Rt_, 1);
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_deleteMMXreg(MMX_GPR+_Rt_, 1);
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MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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MOV32RtoM( (uptr)&fpuRegs.fprc[ _Fs_ ], EAX );
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}
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}
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}
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}
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// MFC1
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//------------------------------------------------------------------
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void recMFC1(void)
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{
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int regt, regs;
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if ( ! _Rt_ ) return;
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_eeOnWriteReg(_Rt_, 1);
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regs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
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if( regs >= 0 )
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{
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_deleteGPRtoXMMreg(_Rt_, 2);
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regt = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_WRITE);
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if( regt >= 0 )
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{
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SSE2_MOVDQ2Q_XMM_to_MM(regt, regs);
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if(EEINST_ISLIVE1(_Rt_))
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_signExtendGPRtoMMX(regt, _Rt_, 0);
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else
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EEINST_RESETHASLIVE1(_Rt_);
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}
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else
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{
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if(EEINST_ISLIVE1(_Rt_))
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{
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_signExtendXMMtoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], regs, 0);
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}
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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SSE_MOVSS_XMM_to_M32((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], regs);
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}
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}
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}
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else
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{
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regs = _checkMMXreg(MMX_FPU+_Fs_, MODE_READ);
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if( regs >= 0 )
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{
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// convert to mmx reg
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mmxregs[regs].reg = MMX_GPR+_Rt_;
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mmxregs[regs].mode |= MODE_READ|MODE_WRITE;
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_signExtendGPRtoMMX(regs, _Rt_, 0);
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}
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else
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{
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regt = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( regt >= 0 )
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{
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if( xmmregs[regt].mode & MODE_WRITE )
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{
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SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], regt);
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}
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xmmregs[regt].inuse = 0;
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}
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_deleteEEreg(_Rt_, 0);
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MOV32MtoR( EAX, (uptr)&fpuRegs.fpr[ _Fs_ ].UL );
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if(EEINST_ISLIVE1(_Rt_))
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{
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CDQ( );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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}
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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}
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}
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}
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}
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// MTC1
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//------------------------------------------------------------------
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void recMTC1(void)
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{
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if( GPR_IS_CONST1(_Rt_) )
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{
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_deleteFPtoXMMreg(_Fs_, 0);
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MOV32ItoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, g_cpuConstRegs[_Rt_].UL[0]);
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}
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else
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{
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int mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( mmreg >= 0 )
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{
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if( g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE )
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{
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// transfer the reg directly
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_deleteGPRtoXMMreg(_Rt_, 2);
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_deleteFPtoXMMreg(_Fs_, 2);
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_allocFPtoXMMreg(mmreg, _Fs_, MODE_WRITE);
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}
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else
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{
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int mmreg2 = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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if( mmreg2 >= 0 )
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SSE_MOVSS_XMM_to_XMM(mmreg2, mmreg);
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else
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SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[ _Fs_ ].UL, mmreg);
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}
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}
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else
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{
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int mmreg2;
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mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ);
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mmreg2 = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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if( mmreg >= 0 )
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{
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if( mmreg2 >= 0 )
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{
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(mmreg2, mmreg);
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}
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else
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{
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SetMMXstate();
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MOVDMMXtoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, mmreg);
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}
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}
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else
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{
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if( mmreg2 >= 0 )
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{
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SSE_MOVSS_M32_to_XMM(mmreg2, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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}
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else
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{
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MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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MOV32RtoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, EAX);
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}
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}
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}
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}
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}
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//------------------------------------------------------------------
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/*#ifndef FPU_RECOMPILE // If FPU_RECOMPILE is not defined, then use the interpreter opcodes. (CFC1, CTC1, MFC1, and MTC1 are special because they work specifically with the EE rec so they're defined above)
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REC_FPUFUNC(ABS_S);
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REC_FPUFUNC(ADD_S);
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REC_FPUFUNC(ADDA_S);
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REC_FPUBRANCH(BC1F);
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REC_FPUBRANCH(BC1T);
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REC_FPUBRANCH(BC1FL);
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REC_FPUBRANCH(BC1TL);
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REC_FPUFUNC(C_EQ);
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REC_FPUFUNC(C_F);
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REC_FPUFUNC(C_LE);
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REC_FPUFUNC(C_LT);
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REC_FPUFUNC(CVT_S);
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REC_FPUFUNC(CVT_W);
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REC_FPUFUNC(DIV_S);
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REC_FPUFUNC(MAX_S);
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REC_FPUFUNC(MIN_S);
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REC_FPUFUNC(MADD_S);
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REC_FPUFUNC(MADDA_S);
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REC_FPUFUNC(MOV_S);
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REC_FPUFUNC(MSUB_S);
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REC_FPUFUNC(MSUBA_S);
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REC_FPUFUNC(MUL_S);
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REC_FPUFUNC(MULA_S);
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REC_FPUFUNC(NEG_S);
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REC_FPUFUNC(SUB_S);
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REC_FPUFUNC(SUBA_S);
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REC_FPUFUNC(SQRT_S);
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REC_FPUFUNC(RSQRT_S);
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#else // FPU_RECOMPILE*/
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//------------------------------------------------------------------
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// PS2 -> DOUBLE
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//------------------------------------------------------------------
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@ -678,7 +418,7 @@ void FPU_MUL(int info, int regd, int sreg, int treg, bool acc)
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// CommutativeOp XMM (used for ADD, MUL, MAX, MIN and SUB opcodes)
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//------------------------------------------------------------------
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static void (*recFPUOpXMM_to_XMM[] )(x86SSERegType, x86SSERegType) = {
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SSE2_ADDSD_XMM_to_XMM, NULL, SSE2_MAXSD_XMM_to_XMM, SSE2_MINSD_XMM_to_XMM, SSE2_SUBSD_XMM_to_XMM };
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SSE2_ADDSD_XMM_to_XMM, NULL, NULL, NULL, SSE2_SUBSD_XMM_to_XMM };
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void recFPUOp(int info, int regd, int op, bool acc)
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{
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@ -718,48 +458,6 @@ void recADDA_S_xmm(int info)
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FPURECOMPILE_CONSTCODE(ADDA_S, XMMINFO_WRITEACC|XMMINFO_READS|XMMINFO_READT);
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// BC1x XMM
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//------------------------------------------------------------------
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/*
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static void _setupBranchTest()
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{
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_eeFlushAllUnused();
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// COP1 branch conditionals are based on the following equation:
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// (fpuRegs.fprc[31] & 0x00800000)
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// BC2F checks if the statement is false, BC2T checks if the statement is true.
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MOV32MtoR(EAX, (uptr)&fpuRegs.fprc[31]);
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TEST32ItoR(EAX, FPUflagC);
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}
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void recBC1F( void )
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{
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_setupBranchTest();
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recDoBranchImm(JNZ32(0));
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}
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void recBC1T( void )
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{
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_setupBranchTest();
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recDoBranchImm(JZ32(0));
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}
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void recBC1FL( void )
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{
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_setupBranchTest();
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recDoBranchImm_Likely(JNZ32(0));
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}
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void recBC1TL( void )
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{
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_setupBranchTest();
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recDoBranchImm_Likely(JZ32(0));
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}*/
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//------------------------------------------------------------------
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//TOKNOW : how does C.??.S behave with denormals?
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void recCMP(int info)
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{
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int sreg, treg;
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@ -788,11 +486,6 @@ void recC_EQ_xmm(int info)
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FPURECOMPILE_CONSTCODE(C_EQ, XMMINFO_READS|XMMINFO_READT);
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/*void recC_F()
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{
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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}*/
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void recC_LE_xmm(int info )
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{
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recCMP(info);
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@ -806,7 +499,6 @@ void recC_LE_xmm(int info )
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}
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FPURECOMPILE_CONSTCODE(C_LE, XMMINFO_READS|XMMINFO_READT);
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//REC_FPUFUNC(C_LE);
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void recC_LT_xmm(int info)
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{
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@ -821,7 +513,6 @@ void recC_LT_xmm(int info)
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}
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FPURECOMPILE_CONSTCODE(C_LT, XMMINFO_READS|XMMINFO_READT);
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//REC_FPUFUNC(C_LT);
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//------------------------------------------------------------------
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@ -840,7 +531,7 @@ void recCVT_S_xmm(int info)
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FPURECOMPILE_CONSTCODE(CVT_S, XMMINFO_WRITED|XMMINFO_READS);
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void recCVT_W()
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void recCVT_W() //called from iFPU.cpp's recCVT_W
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{
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int regs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
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@ -1052,17 +743,42 @@ FPURECOMPILE_CONSTCODE(MADDA_S, XMMINFO_WRITEACC|XMMINFO_READACC|XMMINFO_READS|X
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// MAX / MIN XMM
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//------------------------------------------------------------------
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//TOKNOW : handles denormals like VU, maybe?
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static const u32 PCSX2_ALIGNED16(minmax_mask[4]) = {0xffffffff, 0x80000000, 0, 0};
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static const u32 PCSX2_ALIGNED16(minmax_mask2[4]) = {0, 0x40000000, 0, 0};
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// FPU's MAX/MIN work with all numbers (including "denormals"). Check VU's logical min max for more info.
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void recMINMAX(int info, bool ismin)
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{
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int sreg, treg;
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ALLOC_S(sreg); ALLOC_T(treg);
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CLEAR_OU_FLAGS;
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SSE2_PSHUFD_XMM_to_XMM(sreg, sreg, 0x00);
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SSE2_PAND_M128_to_XMM(sreg, (uptr)minmax_mask);
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SSE2_POR_M128_to_XMM(sreg, (uptr)minmax_mask2);
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SSE2_PSHUFD_XMM_to_XMM(treg, treg, 0x00);
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SSE2_PAND_M128_to_XMM(treg, (uptr)minmax_mask);
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SSE2_POR_M128_to_XMM(treg, (uptr)minmax_mask2);
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if (ismin)
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SSE2_MINSD_XMM_to_XMM(sreg, treg);
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else
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SSE2_MAXSD_XMM_to_XMM(sreg, treg);
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SSE_MOVSS_XMM_to_XMM(EEREC_D, sreg);
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_freeXMMreg(sreg); _freeXMMreg(treg);
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}
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void recMAX_S_xmm(int info)
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{
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recFPUOp(info, EEREC_D, 2, false);
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recMINMAX(info, false);
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}
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FPURECOMPILE_CONSTCODE(MAX_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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void recMIN_S_xmm(int info)
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{
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recFPUOp(info, EEREC_D, 3, false);
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recMINMAX(info, true);
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}
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FPURECOMPILE_CONSTCODE(MIN_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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@ -1322,6 +1038,5 @@ void recRSQRT_S_xmm(int info)
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FPURECOMPILE_CONSTCODE(RSQRT_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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//#endif // FPU_RECOMPILE
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} } } } }
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