mirror of https://github.com/PCSX2/pcsx2.git
Fix for GTC Africa Jerkyness (Placement issue), Fix for Aura for Laura demo causing graphical errors, was multiplying VU Cycles by BIAS twice, not really clever :P
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4239 96395faa-99c1-11dd-bbfe-3dabce05a288
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2382c35b83
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@ -163,8 +163,30 @@ __fi void vif0Interrupt()
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g_vifCycles = 0;
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vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8);
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if (!(vif0ch.chcr.STR)) Console.WriteLn("vif0 running when CHCR == %x", vif0ch.chcr._u32);
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if (vif0.irq && vif0.tag.size == 0)
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{
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vif0Regs.stat.INT = true;
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hwIntcIrq(VIF0intc);
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--vif0.irq;
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if (vif0Regs.stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
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{
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//vif0Regs.stat.FQC = 0;
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// One game doesn't like vif stalling at end, can't remember what. Spiderman isn't keen on it tho
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//vif0ch.chcr.STR = false;
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if(vif0ch.qwc > 0 || !vif0.done)
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{
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VIF_LOG("VIF0 Stalled");
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return;
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}
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}
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}
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//Must go after the Stall, incase it's still in progress, GTC africa likes to see it still transferring.
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if (vif0.cmd)
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{
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if(vif0.done == true && vif0ch.qwc == 0) vif0Regs.stat.VPS = VPS_WAITING;
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@ -174,24 +196,10 @@ __fi void vif0Interrupt()
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vif0Regs.stat.VPS = VPS_IDLE;
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}
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if (vif0.irq && vif0.tag.size == 0)
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{
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vif0Regs.stat.INT = true;
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hwIntcIrq(VIF0intc);
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--vif0.irq;
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if (vif0Regs.stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
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{
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vif0Regs.stat.FQC = 0;
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// One game doesn't like vif stalling at end, can't remember what. Spiderman isn't keen on it tho
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//vif0ch.chcr.STR = false;
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if(vif0ch.qwc > 0 || !vif0.done) return;
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}
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}
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if (vif0.inprogress & 0x1)
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{
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_VIF0chain();
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vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8);
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CPU_INT(DMAC_VIF0, g_vifCycles);
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return;
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}
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@ -206,7 +214,7 @@ __fi void vif0Interrupt()
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}
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if ((vif0.inprogress & 0x1) == 0) vif0SetupTransfer();
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vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8);
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CPU_INT(DMAC_VIF0, g_vifCycles);
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return;
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}
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@ -373,17 +373,9 @@ __fi void vif1Interrupt()
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if (!vif1ch.chcr.STR) Console.WriteLn("Vif1 running when CHCR == %x", vif1ch.chcr._u32);
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if (vif1.cmd)
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{
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if (vif1.done && (vif1ch.qwc == 0)) vif1Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif1Regs.stat.VPS = VPS_IDLE;
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}
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if (vif1.irq && vif1.tag.size == 0)
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{
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VIF_LOG("VIF IRQ Firing");
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vif1Regs.stat.INT = true;
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hwIntcIrq(VIF1intc);
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--vif1.irq;
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@ -393,10 +385,24 @@ __fi void vif1Interrupt()
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//NFSHPS stalls when the whole packet has gone across (it stalls in the last 32bit cmd)
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//In this case VIF will end
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if(vif1ch.qwc > 0 || !vif1.done) return;
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if(vif1ch.qwc > 0 || !vif1.done)
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{
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VIF_LOG("VIF1 Stalled");
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return;
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}
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}
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}
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//Mirroring change to VIF0
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if (vif1.cmd)
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{
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if (vif1.done && (vif1ch.qwc == 0)) vif1Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif1Regs.stat.VPS = VPS_IDLE;
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}
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if (vif1.inprogress & 0x1)
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{
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_VIF1chain();
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@ -124,7 +124,7 @@ static __fi void mfifo_VIF1chain()
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if (vif1ch.madr >= dmacRegs.rbor.ADDR &&
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vif1ch.madr <= (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16))
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{
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if(vif1ch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) DevCon.Warning("Edge VIF1");
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//if(vif1ch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) DevCon.Warning("Edge VIF1");
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vif1ch.madr = qwctag(vif1ch.madr);
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mfifoVIF1rbTransfer();
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@ -281,16 +281,6 @@ void vifMFIFOInterrupt()
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//Simulated GS transfer time done, clear the flags
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if (vif1.cmd)
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{
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if(vif1.done == true && vif1ch.qwc == 0) vif1Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif1Regs.stat.VPS = VPS_IDLE;
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}
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if (vif1.irq && vif1.tag.size == 0)
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{
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SPR_LOG("VIF MFIFO Code Interrupt detected");
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@ -302,10 +292,24 @@ void vifMFIFOInterrupt()
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{
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/*vif1Regs.stat.FQC = 0; // FQC=0
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vif1ch.chcr.STR = false;*/
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if((vif1ch.qwc > 0 || !vif1.done) && !(vif1.inprogress & 0x10)) return;
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if((vif1ch.qwc > 0 || !vif1.done) && !(vif1.inprogress & 0x10))
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{
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VIF_LOG("VIF1 MFIFO Stalled");
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return;
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}
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}
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}
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//Mirroring change to VIF0
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if (vif1.cmd)
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{
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if(vif1.done == true && vif1ch.qwc == 0) vif1Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif1Regs.stat.VPS = VPS_IDLE;
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}
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if(vif1.inprogress & 0x10)
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{
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FireMFIFOEmpty();
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@ -74,9 +74,9 @@ static __fi void vuExecMicro(int idx, u32 addr) {
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if (!idx) vu0ExecMicro(addr);
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else vu1ExecMicro(addr);
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if(!idx) { g_vu0Cycles += (VU0.cycle-startcycles) * BIAS; g_packetsizeonvu = vif0.vifpacketsize; }
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else { g_vu1Cycles += (VU1.cycle-startcycles) * BIAS; g_packetsizeonvu = vif1.vifpacketsize; }
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//DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x", idx, g_vu0Cycles, g_vu1Cycles);
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if(!idx) { g_vu0Cycles += (VU0.cycle-startcycles); g_packetsizeonvu = vif0.vifpacketsize; }
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else { g_vu1Cycles += (VU1.cycle-startcycles); g_packetsizeonvu = vif1.vifpacketsize; }
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//DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x, start %x cycle %x", idx, g_vu0Cycles, g_vu1Cycles, startcycles, VU1.cycle);
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GetVifX.vifstalled = true;
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}
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