From 07bb54acc4dfaa48e9a35b27783bac25e69072e5 Mon Sep 17 00:00:00 2001 From: refraction Date: Fri, 21 Jan 2011 15:17:29 +0000 Subject: [PATCH] Fix for GTC Africa Jerkyness (Placement issue), Fix for Aura for Laura demo causing graphical errors, was multiplying VU Cycles by BIAS twice, not really clever :P git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4239 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/Vif0_Dma.cpp | 40 ++++++++++++++++++++++++---------------- pcsx2/Vif1_Dma.cpp | 26 ++++++++++++++++---------- pcsx2/Vif1_MFIFO.cpp | 28 ++++++++++++++++------------ pcsx2/Vif_Codes.cpp | 6 +++--- 4 files changed, 59 insertions(+), 41 deletions(-) diff --git a/pcsx2/Vif0_Dma.cpp b/pcsx2/Vif0_Dma.cpp index fc5fed0682..0a83c2ff56 100644 --- a/pcsx2/Vif0_Dma.cpp +++ b/pcsx2/Vif0_Dma.cpp @@ -163,8 +163,30 @@ __fi void vif0Interrupt() g_vifCycles = 0; + vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8); + if (!(vif0ch.chcr.STR)) Console.WriteLn("vif0 running when CHCR == %x", vif0ch.chcr._u32); + if (vif0.irq && vif0.tag.size == 0) + { + vif0Regs.stat.INT = true; + hwIntcIrq(VIF0intc); + --vif0.irq; + if (vif0Regs.stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS)) + { + //vif0Regs.stat.FQC = 0; + + // One game doesn't like vif stalling at end, can't remember what. Spiderman isn't keen on it tho + //vif0ch.chcr.STR = false; + if(vif0ch.qwc > 0 || !vif0.done) + { + VIF_LOG("VIF0 Stalled"); + return; + } + } + } + + //Must go after the Stall, incase it's still in progress, GTC africa likes to see it still transferring. if (vif0.cmd) { if(vif0.done == true && vif0ch.qwc == 0) vif0Regs.stat.VPS = VPS_WAITING; @@ -174,24 +196,10 @@ __fi void vif0Interrupt() vif0Regs.stat.VPS = VPS_IDLE; } - if (vif0.irq && vif0.tag.size == 0) - { - vif0Regs.stat.INT = true; - hwIntcIrq(VIF0intc); - --vif0.irq; - if (vif0Regs.stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS)) - { - vif0Regs.stat.FQC = 0; - - // One game doesn't like vif stalling at end, can't remember what. Spiderman isn't keen on it tho - //vif0ch.chcr.STR = false; - if(vif0ch.qwc > 0 || !vif0.done) return; - } - } - if (vif0.inprogress & 0x1) { _VIF0chain(); + vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8); CPU_INT(DMAC_VIF0, g_vifCycles); return; } @@ -206,7 +214,7 @@ __fi void vif0Interrupt() } if ((vif0.inprogress & 0x1) == 0) vif0SetupTransfer(); - + vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8); CPU_INT(DMAC_VIF0, g_vifCycles); return; } diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp index 306ec29c0a..e79214225e 100644 --- a/pcsx2/Vif1_Dma.cpp +++ b/pcsx2/Vif1_Dma.cpp @@ -373,17 +373,9 @@ __fi void vif1Interrupt() if (!vif1ch.chcr.STR) Console.WriteLn("Vif1 running when CHCR == %x", vif1ch.chcr._u32); - if (vif1.cmd) - { - if (vif1.done && (vif1ch.qwc == 0)) vif1Regs.stat.VPS = VPS_WAITING; - } - else - { - vif1Regs.stat.VPS = VPS_IDLE; - } - if (vif1.irq && vif1.tag.size == 0) { + VIF_LOG("VIF IRQ Firing"); vif1Regs.stat.INT = true; hwIntcIrq(VIF1intc); --vif1.irq; @@ -393,10 +385,24 @@ __fi void vif1Interrupt() //NFSHPS stalls when the whole packet has gone across (it stalls in the last 32bit cmd) //In this case VIF will end - if(vif1ch.qwc > 0 || !vif1.done) return; + if(vif1ch.qwc > 0 || !vif1.done) + { + VIF_LOG("VIF1 Stalled"); + return; + } } } + //Mirroring change to VIF0 + if (vif1.cmd) + { + if (vif1.done && (vif1ch.qwc == 0)) vif1Regs.stat.VPS = VPS_WAITING; + } + else + { + vif1Regs.stat.VPS = VPS_IDLE; + } + if (vif1.inprogress & 0x1) { _VIF1chain(); diff --git a/pcsx2/Vif1_MFIFO.cpp b/pcsx2/Vif1_MFIFO.cpp index 4142197f37..6bd02bf187 100644 --- a/pcsx2/Vif1_MFIFO.cpp +++ b/pcsx2/Vif1_MFIFO.cpp @@ -124,7 +124,7 @@ static __fi void mfifo_VIF1chain() if (vif1ch.madr >= dmacRegs.rbor.ADDR && vif1ch.madr <= (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) { - if(vif1ch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) DevCon.Warning("Edge VIF1"); + //if(vif1ch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) DevCon.Warning("Edge VIF1"); vif1ch.madr = qwctag(vif1ch.madr); mfifoVIF1rbTransfer(); @@ -281,16 +281,6 @@ void vifMFIFOInterrupt() //Simulated GS transfer time done, clear the flags - if (vif1.cmd) - { - if(vif1.done == true && vif1ch.qwc == 0) vif1Regs.stat.VPS = VPS_WAITING; - } - else - { - vif1Regs.stat.VPS = VPS_IDLE; - } - - if (vif1.irq && vif1.tag.size == 0) { SPR_LOG("VIF MFIFO Code Interrupt detected"); @@ -302,10 +292,24 @@ void vifMFIFOInterrupt() { /*vif1Regs.stat.FQC = 0; // FQC=0 vif1ch.chcr.STR = false;*/ - if((vif1ch.qwc > 0 || !vif1.done) && !(vif1.inprogress & 0x10)) return; + if((vif1ch.qwc > 0 || !vif1.done) && !(vif1.inprogress & 0x10)) + { + VIF_LOG("VIF1 MFIFO Stalled"); + return; + } } } + //Mirroring change to VIF0 + if (vif1.cmd) + { + if(vif1.done == true && vif1ch.qwc == 0) vif1Regs.stat.VPS = VPS_WAITING; + } + else + { + vif1Regs.stat.VPS = VPS_IDLE; + } + if(vif1.inprogress & 0x10) { FireMFIFOEmpty(); diff --git a/pcsx2/Vif_Codes.cpp b/pcsx2/Vif_Codes.cpp index 1aa4c23928..708ac46c16 100644 --- a/pcsx2/Vif_Codes.cpp +++ b/pcsx2/Vif_Codes.cpp @@ -74,9 +74,9 @@ static __fi void vuExecMicro(int idx, u32 addr) { if (!idx) vu0ExecMicro(addr); else vu1ExecMicro(addr); - if(!idx) { g_vu0Cycles += (VU0.cycle-startcycles) * BIAS; g_packetsizeonvu = vif0.vifpacketsize; } - else { g_vu1Cycles += (VU1.cycle-startcycles) * BIAS; g_packetsizeonvu = vif1.vifpacketsize; } - //DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x", idx, g_vu0Cycles, g_vu1Cycles); + if(!idx) { g_vu0Cycles += (VU0.cycle-startcycles); g_packetsizeonvu = vif0.vifpacketsize; } + else { g_vu1Cycles += (VU1.cycle-startcycles); g_packetsizeonvu = vif1.vifpacketsize; } + //DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x, start %x cycle %x", idx, g_vu0Cycles, g_vu1Cycles, startcycles, VU1.cycle); GetVifX.vifstalled = true; }