mirror of https://github.com/PCSX2/pcsx2.git
One last pass on the register freezing code for now, and remove the remnants of the iVif workaround code.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2060 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
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1a09a7792f
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06d3e01efe
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@ -15,6 +15,8 @@
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#pragma once
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#include "x86emitter.h"
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// this is all that needs to be called and will fill up the below structs
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extern void cpudetectInit();
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@ -104,6 +106,7 @@ namespace MMXRegisters
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extern void Freeze();
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extern void Thaw();
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extern bool Saved();
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extern __aligned16 u64 data[8];
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};
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namespace XMMRegisters
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@ -111,6 +114,7 @@ namespace XMMRegisters
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extern void Freeze();
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extern void Thaw();
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extern bool Saved();
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extern __aligned16 u64 data[2*iREGCNT_XMM];
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};
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namespace Registers
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@ -14,14 +14,11 @@
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*/
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#include "PrecompiledHeader.h"
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#include "internal.h"
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#include "tools.h"
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// To make sure regs don't get changed while in the recompiler,
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// use Freeze/Thaw in MMXRegisters, XMMRegisters, & Registers.
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__aligned16 u64 g_globalMMXData[8];
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__aligned16 u64 g_globalXMMData[2*iREGCNT_XMM];
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/////////////////////////////////////////////////////////////////////
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// MMX Register Freezing
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@ -30,6 +27,7 @@ __aligned16 u64 g_globalXMMData[2*iREGCNT_XMM];
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namespace MMXRegisters
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{
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u8 stack_depth = 0;
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__aligned16 u64 data[8];
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__forceinline bool Saved()
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{
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@ -51,7 +49,7 @@ namespace MMXRegisters
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#ifdef _MSC_VER
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__asm {
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mov ecx, offset g_globalMMXData
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mov ecx, offset data
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movntq mmword ptr [ecx+0], mm0
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movntq mmword ptr [ecx+8], mm1
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movntq mmword ptr [ecx+16], mm2
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@ -65,16 +63,16 @@ namespace MMXRegisters
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#else
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movq [%[g_globalMMXData]+0x00], mm0\n"
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"movq [%[g_globalMMXData]+0x08], mm1\n"
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"movq [%[g_globalMMXData]+0x10], mm2\n"
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"movq [%[g_globalMMXData]+0x18], mm3\n"
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"movq [%[g_globalMMXData]+0x20], mm4\n"
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"movq [%[g_globalMMXData]+0x28], mm5\n"
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"movq [%[g_globalMMXData]+0x30], mm6\n"
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"movq [%[g_globalMMXData]+0x38], mm7\n"
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"movq [%[data]+0x00], mm0\n"
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"movq [%[data]+0x08], mm1\n"
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"movq [%[data]+0x10], mm2\n"
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"movq [%[data]+0x18], mm3\n"
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"movq [%[data]+0x20], mm4\n"
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"movq [%[data]+0x28], mm5\n"
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"movq [%[data]+0x30], mm6\n"
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"movq [%[data]+0x38], mm7\n"
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"emms\n"
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".att_syntax\n" : : [g_globalMMXData]"r"(g_globalMMXData) : "memory"
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".att_syntax\n" : : [data]"r"(data) : "memory"
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);
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#endif
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}
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@ -96,7 +94,7 @@ namespace MMXRegisters
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#ifdef _MSC_VER
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__asm {
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mov ecx, offset g_globalMMXData
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mov ecx, offset data
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movq mm0, mmword ptr [ecx+0]
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movq mm1, mmword ptr [ecx+8]
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movq mm2, mmword ptr [ecx+16]
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@ -110,16 +108,16 @@ namespace MMXRegisters
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#else
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movq mm0, [%[g_globalMMXData]+0x00]\n"
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"movq mm1, [%[g_globalMMXData]+0x08]\n"
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"movq mm2, [%[g_globalMMXData]+0x10]\n"
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"movq mm3, [%[g_globalMMXData]+0x18]\n"
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"movq mm4, [%[g_globalMMXData]+0x20]\n"
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"movq mm5, [%[g_globalMMXData]+0x28]\n"
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"movq mm6, [%[g_globalMMXData]+0x30]\n"
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"movq mm7, [%[g_globalMMXData]+0x38]\n"
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"movq mm0, [%[data]+0x00]\n"
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"movq mm1, [%[data]+0x08]\n"
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"movq mm2, [%[data]+0x10]\n"
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"movq mm3, [%[data]+0x18]\n"
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"movq mm4, [%[data]+0x20]\n"
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"movq mm5, [%[data]+0x28]\n"
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"movq mm6, [%[data]+0x30]\n"
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"movq mm7, [%[data]+0x38]\n"
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"emms\n"
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".att_syntax\n" : : [g_globalMMXData]"r"(g_globalMMXData) : "memory"
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".att_syntax\n" : : [data]"r"(data) : "memory"
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);
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#endif
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}
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@ -132,6 +130,7 @@ namespace MMXRegisters
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namespace XMMRegisters
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{
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u8 stack_depth = 0;
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__aligned16 u64 data[2*iREGCNT_XMM];
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__forceinline bool Saved()
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{
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@ -154,7 +153,7 @@ namespace XMMRegisters
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#ifdef _MSC_VER
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__asm {
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mov ecx, offset g_globalXMMData
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mov ecx, offset data
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movaps xmmword ptr [ecx+0x00], xmm0
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movaps xmmword ptr [ecx+0x10], xmm1
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movaps xmmword ptr [ecx+0x20], xmm2
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@ -167,15 +166,15 @@ namespace XMMRegisters
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#else
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movaps [%[g_globalXMMData]+0x00], xmm0\n"
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"movaps [%[g_globalXMMData]+0x10], xmm1\n"
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"movaps [%[g_globalXMMData]+0x20], xmm2\n"
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"movaps [%[g_globalXMMData]+0x30], xmm3\n"
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"movaps [%[g_globalXMMData]+0x40], xmm4\n"
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"movaps [%[g_globalXMMData]+0x50], xmm5\n"
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"movaps [%[g_globalXMMData]+0x60], xmm6\n"
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"movaps [%[g_globalXMMData]+0x70], xmm7\n"
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".att_syntax\n" : : [g_globalXMMData]"r"(g_globalXMMData) : "memory"
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"movaps [%[data]+0x00], xmm0\n"
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"movaps [%[data]+0x10], xmm1\n"
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"movaps [%[data]+0x20], xmm2\n"
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"movaps [%[data]+0x30], xmm3\n"
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"movaps [%[data]+0x40], xmm4\n"
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"movaps [%[data]+0x50], xmm5\n"
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"movaps [%[data]+0x60], xmm6\n"
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"movaps [%[data]+0x70], xmm7\n"
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".att_syntax\n" : : [data]"r"(data) : "memory"
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);
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#endif // _MSC_VER
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}
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#ifdef _MSC_VER
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__asm
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{
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mov ecx, offset g_globalXMMData
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mov ecx, offset data
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movaps xmm0, xmmword ptr [ecx+0x00]
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movaps xmm1, xmmword ptr [ecx+0x10]
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movaps xmm2, xmmword ptr [ecx+0x20]
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#else
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movaps xmm0, [%[g_globalXMMData]+0x00]\n"
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"movaps xmm1, [%[g_globalXMMData]+0x10]\n"
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"movaps xmm2, [%[g_globalXMMData]+0x20]\n"
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"movaps xmm3, [%[g_globalXMMData]+0x30]\n"
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"movaps xmm4, [%[g_globalXMMData]+0x40]\n"
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"movaps xmm5, [%[g_globalXMMData]+0x50]\n"
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"movaps xmm6, [%[g_globalXMMData]+0x60]\n"
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"movaps xmm7, [%[g_globalXMMData]+0x70]\n"
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".att_syntax\n" : : [g_globalXMMData]"r"(g_globalXMMData) : "memory"
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"movaps xmm0, [%[data]+0x00]\n"
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"movaps xmm1, [%[data]+0x10]\n"
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"movaps xmm2, [%[data]+0x20]\n"
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"movaps xmm3, [%[data]+0x30]\n"
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"movaps xmm4, [%[data]+0x40]\n"
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"movaps xmm5, [%[data]+0x50]\n"
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"movaps xmm6, [%[data]+0x60]\n"
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"movaps xmm7, [%[data]+0x70]\n"
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".att_syntax\n" : : [data]"r"(data) : "memory"
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);
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#endif // _MSC_VER
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}
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#include "internal.h"
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// defined in tools.cpp
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extern __aligned16 u64 g_globalXMMData[2*iREGCNT_XMM];
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//extern __aligned16 u64 g_globalXMMData[2*iREGCNT_XMM];
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#include "tools.h"
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// ------------------------------------------------------------------------
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// Notes on Thread Local Storage:
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__emitinline void xStoreReg( const xRegisterSSE& src )
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{
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xMOVDQA( &g_globalXMMData[src.Id*2], src );
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xMOVDQA( &XMMRegisters::data[src.Id*2], src );
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}
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__emitinline void xRestoreReg( const xRegisterSSE& dest )
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{
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xMOVDQA( dest, &g_globalXMMData[dest.Id*2] );
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xMOVDQA( dest, &XMMRegisters::data[dest.Id*2] );
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}
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}
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extern "C" __aligned16 u32 s_TempDecompress[4];
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__aligned16 u32 s_TempDecompress[4] = {0};
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/*#ifdef __LINUX__
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static void __forceinline UseOldMaskCode(u32* &vif1masks, u32 &mask);
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#endif*/
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// Note: this function used to break regularly on Linux due to stack alignment.
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// Refer to old revisions of this code if it breaks again for workarounds.
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void __fastcall SetNewMask(u32* vif1masks, u32* hasmask, u32 mask, u32 oldmask)
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{
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u32 i;
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hasmask[i] = prev;
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if ((mask&0xff) != (oldmask&0xff))
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//#ifdef __LINUX__
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// This seems to now be hitting several games, and not just in that spot,
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// so until we can work out something better, I'm reverting to using the
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// old Linux mask code all the time. --arcum42
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// Note: not neccessary if we set -mpreferred-stack-boundary=2, so it is now
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// disabled.
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//if (mask == 0) // Temporary workaround for a bug causing a segfault.
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//UseOldMaskCode(vif1masks, mask);
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//else
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//#else
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{
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__m128i r0, r1, r2, r3;
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r0 = _mm_load_si128((__m128i*)&s_maskarr[mask&15][0]); // Tends to crash Linux,
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_mm_storeh_pi((__m64*)&vif1masks[12], *(__m128*)&r2);
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_mm_storeh_pi((__m64*)&vif1masks[14], *(__m128*)&r3);
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}
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//#endif
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}
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XMMRegisters::Thaw();
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}
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/*#ifdef __LINUX__
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static void __forceinline UseOldMaskCode(u32* &vif1masks, u32 &mask)
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{
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u8* p0 = (u8*)&s_maskarr[mask&15][0];
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u8* p1 = (u8*)&s_maskarr[(mask>>4)&15][0];
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__asm__ __volatile__(".intel_syntax noprefix\n"
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"movaps xmm0, [%0]\n"
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"movaps xmm1, [%1]\n"
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"movaps xmm2, xmm0\n"
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"punpcklwd xmm0, xmm0\n"
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"punpckhwd xmm2, xmm2\n"
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"movaps xmm3, xmm1\n"
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"punpcklwd xmm1, xmm1\n"
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"punpckhwd xmm3, xmm3\n"
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"movq [%2], xmm0\n"
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"movq [%2+8], xmm1\n"
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"movhps [%2+16], xmm0\n"
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"movhps [%2+24], xmm1\n"
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"movq [%2+32], xmm2\n"
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"movq [%2+40], xmm3\n"
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"movhps [%2+48], xmm2\n"
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"movhps [%2+56], xmm3\n"
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".att_syntax\n" : : "r"(p0), "r"(p1), "r"(vif1masks) : "memory" );
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}
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#endif*/
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