mirror of https://github.com/PCSX2/pcsx2.git
Sif: Check if there is anything in the fifo before reading from it, and if there is any free space in it before writing to it. Tweak logging a bit.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2704 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
3f45a3b8b1
commit
02497e0d41
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@ -36,7 +36,7 @@ static _BaseStateThread* current_state_thread = NULL;
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static NonblockingMutex state_buffer_lock;
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// This boolean tracks if a savestate is actively saving. When a state is saving we
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// typically delay program termination to allow th state time to finish it's work.
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// typically delay program termination to allow the state time to finish its work.
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static bool state_is_saving = false;
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// This boolean is to keep the system from resuming emulation until the current state has completely
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@ -18,11 +18,6 @@
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#define FIFO_SIF_W 128
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// I'm not sure if removing the top 8 bits is correct or not, so this define lets me test it a bit.
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// It doesn't seem like word has anything in the first 8 bits anyways, but data does (IRQ and tag id),
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// so I'll have to play with it.
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#define CHOP_OFF_DATA
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struct sifData
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{
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s32 data;
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@ -26,6 +26,7 @@ static bool done = false;
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static __forceinline void Sif0Init()
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{
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SIF_LOG("SIF0 DMA start...");
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done = false;
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sif0.ee.cycles = 0;
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sif0.iop.cycles = 0;
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@ -35,34 +36,28 @@ static __forceinline void Sif0Init()
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static __forceinline bool WriteFifoToEE()
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{
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const int readSize = min((s32)sif0dma->qwc, sif0.fifo.size >> 2);
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//if (readSize > 0)
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//{
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tDMA_TAG *ptag;
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tDMA_TAG *ptag;
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
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SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif0dma->qwc << 2);
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
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SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif0dma->qwc << 2);
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ptag = sif0dma->getAddr(sif0dma->madr, DMAC_SIF0);
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if (ptag == NULL)
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{
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DevCon.Warning("Write Fifo to EE: ptag == NULL");
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return false;
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}
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ptag = sif0dma->getAddr(sif0dma->madr, DMAC_SIF0);
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if (ptag == NULL)
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{
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DevCon.Warning("Write Fifo to EE: ptag == NULL");
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return false;
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}
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sif0.fifo.read((u32*)ptag, readSize << 2);
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sif0.fifo.read((u32*)ptag, readSize << 2);
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// Clearing handled by vtlb memory protection and manual blocks.
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//Cpu->Clear(sif0dma->madr, readSize*4);
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// Clearing handled by vtlb memory protection and manual blocks.
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//Cpu->Clear(sif0dma->madr, readSize*4);
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sif0dma->madr += readSize << 4;
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sif0.ee.cycles += readSize; // fixme : BIAS is factored in above
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sif0dma->qwc -= readSize;
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//}
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//else
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//{
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//DevCon.Warning("Write Fifo to EE: readSize is 0");
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// return false;
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//}
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sif0dma->madr += readSize << 4;
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sif0.ee.cycles += readSize; // fixme : BIAS is factored in above
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sif0dma->qwc -= readSize;
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return true;
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}
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@ -72,13 +67,6 @@ static __forceinline bool WriteIOPtoFifo()
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// There's some data ready to transfer into the fifo..
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const int writeSize = min(sif0.iop.counter, sif0.fifo.free());
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//if (writeSize <= 0)
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//{
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//DevCon.Warning("Write IOP to Fifo: writeSize is 0");
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// return false;
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//}
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//else
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//{
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SIF_LOG("Write IOP to Fifo: +++++++++++ %lX of %lX", writeSize, sif0.iop.counter);
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sif0.fifo.write((u32*)iopPhysMem(hw_dma(9).madr), writeSize);
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@ -87,7 +75,7 @@ static __forceinline bool WriteIOPtoFifo()
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords).
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sif0.iop.cycles += (writeSize >> 2) * BIAS; // fixme : should be >> 4
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sif0.iop.counter -= writeSize;
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//}
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return true;
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}
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@ -142,17 +130,13 @@ static __forceinline bool ProcessIOPTag()
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hw_dma(9).tadr += 16; ///hw_dma(9).madr + 16 + sif0.sifData.words << 2;
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// Looks like we are only copying the first 24 bits.
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#ifdef CHOP_OFF_DATA
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// We're only copying the first 24 bits.
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hw_dma(9).madr = sif0data & 0xFFFFFF;
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#else
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hw_dma(9).madr = sif0data;
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#endif
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sif0.iop.counter = sif0words;
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//if (sif0words != ( sif0words & 0xFFFFFF)) DevCon.WriteLn("sif0words more then 24 bit.");
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if (sif0tag.IRQ || (sif0tag.ID & 4)) sif0.iop.end = true;
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SIF_LOG("SIF0 IOP Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", hw_dma(9).madr, hw_dma(9).tadr, sif0.iop.counter, sif0words, sif0data);
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return true;
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}
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@ -164,7 +148,7 @@ static __forceinline void EndEE()
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sif0.ee.busy = false;
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if (sif0.ee.cycles == 0)
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{
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DevCon.Warning("SIF0 EE: cycles = 0");
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SIF_LOG("SIF0 EE: cycles = 0");
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sif0.ee.cycles = 1;
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}
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CPU_INT(DMAC_SIF0, sif0.ee.cycles*BIAS);
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@ -180,7 +164,7 @@ static __forceinline void EndIOP()
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if (sif0.iop.cycles == 0)
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{
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DevCon.Warning("SIF0 IOP: cycles = 0");
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SIF_LOG("SIF0 IOP: cycles = 0");
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sif0.iop.cycles = 1;
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}
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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@ -218,7 +202,10 @@ static __forceinline void HandleEETransfer()
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if (sif0dma->qwc > 0) // If we're writing something, continue to do so.
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{
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// Write from Fifo to EE.
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WriteFifoToEE();
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if (sif0.fifo.size > 0)
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{
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WriteFifoToEE();
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}
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}
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}
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@ -271,18 +258,21 @@ static __forceinline void HandleIOPTransfer()
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else
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{
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// Write IOP to Fifo.
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WriteIOPtoFifo();
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if (sif0.fifo.free() > 0)
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{
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WriteIOPtoFifo();
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}
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}
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}
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static __forceinline void Sif0End()
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{
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SIF_LOG("SIF0 DMA end...");
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}
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// Transfer IOP to EE, putting data in the fifo as an intermediate step.
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__forceinline void SIF0Dma()
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{
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SIF_LOG("SIF0 DMA start...");
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Sif0Init();
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do
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@ -291,7 +281,6 @@ __forceinline void SIF0Dma()
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if (sif0.ee.busy) HandleEETransfer();
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} while (!done); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
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SIF_LOG("SIF0 DMA end...");
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Sif0End();
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}
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@ -26,6 +26,7 @@ static bool done = false;
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static __forceinline void Sif1Init()
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{
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SIF_LOG("SIF1 DMA start...");
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done = false;
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sif1.ee.cycles = 0;
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sif1.iop.cycles = 0;
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@ -38,28 +39,22 @@ static __forceinline bool WriteEEtoFifo()
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SIF_LOG("Sif 1: Write EE to Fifo");
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const int writeSize = min((s32)sif1dma->qwc, sif1.fifo.free() >> 2);
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//if (writeSize <= 0)
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//{
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//DevCon.Warning("WriteEEtoFifo: writeSize is 0");
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// return false;
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//}
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//else
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//{
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tDMA_TAG *ptag;
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tDMA_TAG *ptag;
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ptag = sif1dma->getAddr(sif1dma->madr, DMAC_SIF1);
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if (ptag == NULL)
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{
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DevCon.Warning("Write EE to Fifo: ptag == NULL");
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return false;
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}
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ptag = sif1dma->getAddr(sif1dma->madr, DMAC_SIF1);
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if (ptag == NULL)
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{
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DevCon.Warning("Write EE to Fifo: ptag == NULL");
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return false;
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}
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sif1.fifo.write((u32*)ptag, writeSize << 2);
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sif1.fifo.write((u32*)ptag, writeSize << 2);
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sif1dma->madr += writeSize << 4;
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sif1.ee.cycles += writeSize; // fixme : BIAS is factored in above
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sif1dma->qwc -= writeSize;
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//}
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sif1dma->madr += writeSize << 4;
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sif1.ee.cycles += writeSize; // fixme : BIAS is factored in above
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sif1dma->qwc -= writeSize;
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return true;
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}
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@ -70,21 +65,15 @@ static __forceinline bool WriteFifoToIOP()
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SIF_LOG("Sif1: Write Fifo to IOP");
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const int readSize = min (sif1.iop.counter, sif1.fifo.size);
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//if (readSize <= 0)
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//{
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//DevCon.Warning("WriteFifoToIOP: readSize is 0");
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// return false;
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//}
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//else
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//{
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SIF_LOG("Sif 1 IOP doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
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SIF_LOG("Sif 1 IOP doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
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sif1.fifo.read((u32*)iopPhysMem(hw_dma(10).madr), readSize);
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psxCpu->Clear(hw_dma(10).madr, readSize);
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hw_dma(10).madr += readSize << 2;
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sif1.iop.cycles += readSize >> 2; // fixme: should be >> 4
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sif1.iop.counter -= readSize;
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//}
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sif1.fifo.read((u32*)iopPhysMem(hw_dma(10).madr), readSize);
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psxCpu->Clear(hw_dma(10).madr, readSize);
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hw_dma(10).madr += readSize << 2;
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sif1.iop.cycles += readSize >> 2; // fixme: should be >> 4
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sif1.iop.counter -= readSize;
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return true;
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}
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@ -161,15 +150,12 @@ static __forceinline bool SIFIOPReadTag()
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SIF_LOG("SIF 1 IOP: dest chain tag madr:%08X wc:%04X id:%X irq:%d",
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sif1data & 0xffffff, sif1words, sif1tag.ID, sif1tag.IRQ);
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#ifdef CHOP_OFF_DATA
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// Only use the first 24 bits.
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hw_dma(10).madr = sif1data & 0xffffff;
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#else
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hw_dma(10).madr = sif1data;
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#endif
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sif1.iop.counter = sif1words;
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//if (sif1words != ( sif1words & 0xFFFFFF)) DevCon.WriteLn("sif1words more then 24 bit.");
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if (sif1tag.IRQ || (sif1tag.ID & 4)) sif1.iop.end = true;
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return true;
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}
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@ -185,7 +171,7 @@ static __forceinline void EndEE()
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// (Cause of double interrupts on the EE)
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if (sif1.ee.cycles == 0)
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{
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DevCon.Warning("SIF1 EE: cycles = 0");
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SIF_LOG("SIF1 EE: cycles = 0");
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sif1.ee.cycles = 1;
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}
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CPU_INT(DMAC_SIF1, min((int)(sif1.ee.cycles*BIAS), 384));
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@ -205,7 +191,7 @@ static __forceinline void EndIOP()
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//Total cycles over 1024 makes SIF too slow to keep up the sound stream in so3...
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if (sif1.iop.cycles == 0)
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{
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DevCon.Warning("SIF1 IOP: cycles = 0");
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SIF_LOG("SIF1 IOP: cycles = 0");
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sif1.iop.cycles = 1;
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}
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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@ -239,7 +225,10 @@ static __forceinline void HandleEETransfer()
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}
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else
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{
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WriteEEtoFifo();
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if (sif1.fifo.free() > 0)
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{
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WriteEEtoFifo();
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}
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}
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}
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@ -248,7 +237,10 @@ static __forceinline void HandleIOPTransfer()
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{
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if (sif1.iop.counter > 0)
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{
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WriteFifoToIOP();
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if (sif1.fifo.size > 0)
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{
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WriteFifoToIOP();
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}
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}
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if (sif1.iop.counter <= 0)
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@ -269,12 +261,12 @@ static __forceinline void HandleIOPTransfer()
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static __forceinline void Sif1End()
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{
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SIF_LOG("SIF1 DMA end...");
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}
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// Transfer EE to IOP, putting data in the fifo as an intermediate step.
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__forceinline void SIF1Dma()
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{
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SIF_LOG("SIF1 DMA start...");
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Sif1Init();
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do
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@ -283,7 +275,6 @@ __forceinline void SIF1Dma()
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if (sif1.iop.busy) HandleIOPTransfer();
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} while (!done);
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SIF_LOG("SIF1 DMA end...");
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Sif1End();
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}
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