From 02497e0d41eb62c434f1d66db761a039f6cc1165 Mon Sep 17 00:00:00 2001 From: arcum42 Date: Sat, 13 Mar 2010 00:48:02 +0000 Subject: [PATCH] Sif: Check if there is anything in the fifo before reading from it, and if there is any free space in it before writing to it. Tweak logging a bit. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2704 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/RecoverySystem.cpp | 2 +- pcsx2/Sif.h | 5 --- pcsx2/Sif0.cpp | 75 ++++++++++++++++--------------------- pcsx2/Sif1.cpp | 81 ++++++++++++++++++---------------------- 4 files changed, 69 insertions(+), 94 deletions(-) diff --git a/pcsx2/RecoverySystem.cpp b/pcsx2/RecoverySystem.cpp index bfdfaa3e2f..7551bebe1f 100644 --- a/pcsx2/RecoverySystem.cpp +++ b/pcsx2/RecoverySystem.cpp @@ -36,7 +36,7 @@ static _BaseStateThread* current_state_thread = NULL; static NonblockingMutex state_buffer_lock; // This boolean tracks if a savestate is actively saving. When a state is saving we -// typically delay program termination to allow th state time to finish it's work. +// typically delay program termination to allow the state time to finish its work. static bool state_is_saving = false; // This boolean is to keep the system from resuming emulation until the current state has completely diff --git a/pcsx2/Sif.h b/pcsx2/Sif.h index b4e9d47a9f..57d6e7b7d2 100644 --- a/pcsx2/Sif.h +++ b/pcsx2/Sif.h @@ -18,11 +18,6 @@ #define FIFO_SIF_W 128 -// I'm not sure if removing the top 8 bits is correct or not, so this define lets me test it a bit. -// It doesn't seem like word has anything in the first 8 bits anyways, but data does (IRQ and tag id), -// so I'll have to play with it. -#define CHOP_OFF_DATA - struct sifData { s32 data; diff --git a/pcsx2/Sif0.cpp b/pcsx2/Sif0.cpp index 3e125a6c45..bbd178b899 100644 --- a/pcsx2/Sif0.cpp +++ b/pcsx2/Sif0.cpp @@ -26,6 +26,7 @@ static bool done = false; static __forceinline void Sif0Init() { + SIF_LOG("SIF0 DMA start..."); done = false; sif0.ee.cycles = 0; sif0.iop.cycles = 0; @@ -35,34 +36,28 @@ static __forceinline void Sif0Init() static __forceinline bool WriteFifoToEE() { const int readSize = min((s32)sif0dma->qwc, sif0.fifo.size >> 2); - //if (readSize > 0) - //{ - tDMA_TAG *ptag; + + tDMA_TAG *ptag; - //SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr); - SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif0dma->qwc << 2); + //SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr); + SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif0dma->qwc << 2); - ptag = sif0dma->getAddr(sif0dma->madr, DMAC_SIF0); - if (ptag == NULL) - { - DevCon.Warning("Write Fifo to EE: ptag == NULL"); - return false; - } + ptag = sif0dma->getAddr(sif0dma->madr, DMAC_SIF0); + if (ptag == NULL) + { + DevCon.Warning("Write Fifo to EE: ptag == NULL"); + return false; + } - sif0.fifo.read((u32*)ptag, readSize << 2); + sif0.fifo.read((u32*)ptag, readSize << 2); - // Clearing handled by vtlb memory protection and manual blocks. - //Cpu->Clear(sif0dma->madr, readSize*4); + // Clearing handled by vtlb memory protection and manual blocks. + //Cpu->Clear(sif0dma->madr, readSize*4); - sif0dma->madr += readSize << 4; - sif0.ee.cycles += readSize; // fixme : BIAS is factored in above - sif0dma->qwc -= readSize; - //} - //else - //{ - //DevCon.Warning("Write Fifo to EE: readSize is 0"); - // return false; - //} + sif0dma->madr += readSize << 4; + sif0.ee.cycles += readSize; // fixme : BIAS is factored in above + sif0dma->qwc -= readSize; + return true; } @@ -72,13 +67,6 @@ static __forceinline bool WriteIOPtoFifo() // There's some data ready to transfer into the fifo.. const int writeSize = min(sif0.iop.counter, sif0.fifo.free()); - //if (writeSize <= 0) - //{ - //DevCon.Warning("Write IOP to Fifo: writeSize is 0"); - // return false; - //} - //else - //{ SIF_LOG("Write IOP to Fifo: +++++++++++ %lX of %lX", writeSize, sif0.iop.counter); sif0.fifo.write((u32*)iopPhysMem(hw_dma(9).madr), writeSize); @@ -87,7 +75,7 @@ static __forceinline bool WriteIOPtoFifo() // iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords). sif0.iop.cycles += (writeSize >> 2) * BIAS; // fixme : should be >> 4 sif0.iop.counter -= writeSize; - //} + return true; } @@ -142,17 +130,13 @@ static __forceinline bool ProcessIOPTag() hw_dma(9).tadr += 16; ///hw_dma(9).madr + 16 + sif0.sifData.words << 2; - // Looks like we are only copying the first 24 bits. -#ifdef CHOP_OFF_DATA + // We're only copying the first 24 bits. hw_dma(9).madr = sif0data & 0xFFFFFF; -#else - hw_dma(9).madr = sif0data; -#endif sif0.iop.counter = sif0words; - //if (sif0words != ( sif0words & 0xFFFFFF)) DevCon.WriteLn("sif0words more then 24 bit."); if (sif0tag.IRQ || (sif0tag.ID & 4)) sif0.iop.end = true; SIF_LOG("SIF0 IOP Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", hw_dma(9).madr, hw_dma(9).tadr, sif0.iop.counter, sif0words, sif0data); + return true; } @@ -164,7 +148,7 @@ static __forceinline void EndEE() sif0.ee.busy = false; if (sif0.ee.cycles == 0) { - DevCon.Warning("SIF0 EE: cycles = 0"); + SIF_LOG("SIF0 EE: cycles = 0"); sif0.ee.cycles = 1; } CPU_INT(DMAC_SIF0, sif0.ee.cycles*BIAS); @@ -180,7 +164,7 @@ static __forceinline void EndIOP() if (sif0.iop.cycles == 0) { - DevCon.Warning("SIF0 IOP: cycles = 0"); + SIF_LOG("SIF0 IOP: cycles = 0"); sif0.iop.cycles = 1; } // iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords) @@ -218,7 +202,10 @@ static __forceinline void HandleEETransfer() if (sif0dma->qwc > 0) // If we're writing something, continue to do so. { // Write from Fifo to EE. - WriteFifoToEE(); + if (sif0.fifo.size > 0) + { + WriteFifoToEE(); + } } } @@ -271,18 +258,21 @@ static __forceinline void HandleIOPTransfer() else { // Write IOP to Fifo. - WriteIOPtoFifo(); + if (sif0.fifo.free() > 0) + { + WriteIOPtoFifo(); + } } } static __forceinline void Sif0End() { + SIF_LOG("SIF0 DMA end..."); } // Transfer IOP to EE, putting data in the fifo as an intermediate step. __forceinline void SIF0Dma() { - SIF_LOG("SIF0 DMA start..."); Sif0Init(); do @@ -291,7 +281,6 @@ __forceinline void SIF0Dma() if (sif0.ee.busy) HandleEETransfer(); } while (!done); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things. - SIF_LOG("SIF0 DMA end..."); Sif0End(); } diff --git a/pcsx2/Sif1.cpp b/pcsx2/Sif1.cpp index 398ea7f0b9..01e78d8325 100644 --- a/pcsx2/Sif1.cpp +++ b/pcsx2/Sif1.cpp @@ -26,6 +26,7 @@ static bool done = false; static __forceinline void Sif1Init() { + SIF_LOG("SIF1 DMA start..."); done = false; sif1.ee.cycles = 0; sif1.iop.cycles = 0; @@ -38,28 +39,22 @@ static __forceinline bool WriteEEtoFifo() SIF_LOG("Sif 1: Write EE to Fifo"); const int writeSize = min((s32)sif1dma->qwc, sif1.fifo.free() >> 2); - //if (writeSize <= 0) - //{ - //DevCon.Warning("WriteEEtoFifo: writeSize is 0"); - // return false; - //} - //else - //{ - tDMA_TAG *ptag; + + tDMA_TAG *ptag; - ptag = sif1dma->getAddr(sif1dma->madr, DMAC_SIF1); - if (ptag == NULL) - { - DevCon.Warning("Write EE to Fifo: ptag == NULL"); - return false; - } + ptag = sif1dma->getAddr(sif1dma->madr, DMAC_SIF1); + if (ptag == NULL) + { + DevCon.Warning("Write EE to Fifo: ptag == NULL"); + return false; + } - sif1.fifo.write((u32*)ptag, writeSize << 2); + sif1.fifo.write((u32*)ptag, writeSize << 2); - sif1dma->madr += writeSize << 4; - sif1.ee.cycles += writeSize; // fixme : BIAS is factored in above - sif1dma->qwc -= writeSize; - //} + sif1dma->madr += writeSize << 4; + sif1.ee.cycles += writeSize; // fixme : BIAS is factored in above + sif1dma->qwc -= writeSize; + return true; } @@ -70,21 +65,15 @@ static __forceinline bool WriteFifoToIOP() SIF_LOG("Sif1: Write Fifo to IOP"); const int readSize = min (sif1.iop.counter, sif1.fifo.size); - //if (readSize <= 0) - //{ - //DevCon.Warning("WriteFifoToIOP: readSize is 0"); - // return false; - //} - //else - //{ - SIF_LOG("Sif 1 IOP doing transfer %04X to %08X", readSize, HW_DMA10_MADR); + + SIF_LOG("Sif 1 IOP doing transfer %04X to %08X", readSize, HW_DMA10_MADR); - sif1.fifo.read((u32*)iopPhysMem(hw_dma(10).madr), readSize); - psxCpu->Clear(hw_dma(10).madr, readSize); - hw_dma(10).madr += readSize << 2; - sif1.iop.cycles += readSize >> 2; // fixme: should be >> 4 - sif1.iop.counter -= readSize; - //} + sif1.fifo.read((u32*)iopPhysMem(hw_dma(10).madr), readSize); + psxCpu->Clear(hw_dma(10).madr, readSize); + hw_dma(10).madr += readSize << 2; + sif1.iop.cycles += readSize >> 2; // fixme: should be >> 4 + sif1.iop.counter -= readSize; + return true; } @@ -161,15 +150,12 @@ static __forceinline bool SIFIOPReadTag() SIF_LOG("SIF 1 IOP: dest chain tag madr:%08X wc:%04X id:%X irq:%d", sif1data & 0xffffff, sif1words, sif1tag.ID, sif1tag.IRQ); -#ifdef CHOP_OFF_DATA + // Only use the first 24 bits. hw_dma(10).madr = sif1data & 0xffffff; -#else - hw_dma(10).madr = sif1data; -#endif + sif1.iop.counter = sif1words; - //if (sif1words != ( sif1words & 0xFFFFFF)) DevCon.WriteLn("sif1words more then 24 bit."); - if (sif1tag.IRQ || (sif1tag.ID & 4)) sif1.iop.end = true; + return true; } @@ -185,7 +171,7 @@ static __forceinline void EndEE() // (Cause of double interrupts on the EE) if (sif1.ee.cycles == 0) { - DevCon.Warning("SIF1 EE: cycles = 0"); + SIF_LOG("SIF1 EE: cycles = 0"); sif1.ee.cycles = 1; } CPU_INT(DMAC_SIF1, min((int)(sif1.ee.cycles*BIAS), 384)); @@ -205,7 +191,7 @@ static __forceinline void EndIOP() //Total cycles over 1024 makes SIF too slow to keep up the sound stream in so3... if (sif1.iop.cycles == 0) { - DevCon.Warning("SIF1 IOP: cycles = 0"); + SIF_LOG("SIF1 IOP: cycles = 0"); sif1.iop.cycles = 1; } // iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords) @@ -239,7 +225,10 @@ static __forceinline void HandleEETransfer() } else { - WriteEEtoFifo(); + if (sif1.fifo.free() > 0) + { + WriteEEtoFifo(); + } } } @@ -248,7 +237,10 @@ static __forceinline void HandleIOPTransfer() { if (sif1.iop.counter > 0) { - WriteFifoToIOP(); + if (sif1.fifo.size > 0) + { + WriteFifoToIOP(); + } } if (sif1.iop.counter <= 0) @@ -269,12 +261,12 @@ static __forceinline void HandleIOPTransfer() static __forceinline void Sif1End() { + SIF_LOG("SIF1 DMA end..."); } // Transfer EE to IOP, putting data in the fifo as an intermediate step. __forceinline void SIF1Dma() { - SIF_LOG("SIF1 DMA start..."); Sif1Init(); do @@ -283,7 +275,6 @@ __forceinline void SIF1Dma() if (sif1.iop.busy) HandleIOPTransfer(); } while (!done); - SIF_LOG("SIF1 DMA end..."); Sif1End(); }