mirror of https://github.com/PCSX2/pcsx2.git
117 lines
5.0 KiB
C
117 lines
5.0 KiB
C
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#ifndef __DMACMAN_H__
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#define __DMACMAN_H__
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#define DMACMAN_VER 0x101
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////////////////////////////// D_CHCR - DMA Channel Control Register
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#define DMAf_30 0x40000000 // unknown; set on 'to' direction
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#define DMAf_TR 0x01000000 // DMA transfer
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#define DMAf_LI 0x00000400 // Linked list GPU; also SPU & SIF0
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#define DMAf_CO 0x00000200 // Continuous stream
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#define DMAf_08 0x00000100 // unknown
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#define DMAf_DR 0x00000001 // Direction to=0/from=1
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// 31 24 23 16 15 8 7 0
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ķ
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// <20> <20>?<3F> <20> <20> <20> <20> <20>T<EFBFBD> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20>L<EFBFBD>C<EFBFBD>?<3F> <20> <20> <20> <20> <20> <20> <20>D<EFBFBD>
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// <20> <20>?<3F> <20> <20> <20> <20> <20>R<EFBFBD> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20>I<EFBFBD>O<EFBFBD>?<3F> <20> <20> <20> <20> <20> <20> <20>R<EFBFBD>
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ľ
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// 30 24 10 9 8 0
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////////////////////////////// DPCR - DMA Primary Control Register
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ķ
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// <20> 67 <20> DMA 6 <20> DMA 5 <20> DMA 4 <20> DMA 3 <20> DMA 2 <20> DMA 1 <20> DMA 0 <20> 0xBF8010F0 DPCR
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ľ
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ķ
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// <20> <20> DMA85 <20> DMA12 <20> DMA11 <20> DMA10 <20> DMA 9 <20> DMA 8 <20> DMA 7 <20> 0xBF801570 DPCR_
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ľ
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ķ
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// <20> <20> <20> <20> <20> <20> DMA15 <20> DMA14 <20> DMA13 <20> 0xBF8015F0 DPCR__
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ľ
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////////// DPCR
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#define DMAch_MDECin 0
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#define DMAch_MDECout 1
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#define DMAch_GPU 2 // SIF2 both directions
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#define DMAch_CD 3
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#define DMAch_SPU 4
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#define DMAch_PIO 5
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#define DMAch_GPUotc 6
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#define DMAch_67 67 // strange
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////////// DPCR_
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#define DMAch_SPU2 7
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#define DMAch_8 8
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#define DMAch_SIF0 9 // SIFout IOP->EE
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#define DMAch_SIF1 10 // SIFin EE->IOP
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#define DMAch_SIO2in 11
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#define DMAch_SIO2out 12
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#define DMAch_85 85 // stange, very strange
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////////// DPCR__
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#define DMAch_13 13
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#define DMAch_14 14
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#define DMAch_15 15
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int dmacman_start(int argc, char* argv[]); // 0
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int dmacman_deinit(); // 2
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void dmacman_call4_SetD_MADR(unsigned int ch, int value); // 4
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int dmacman_call5_GetD_MADR(unsigned int ch); // 5
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void dmacman_call6_SetD_BCR(unsigned int ch, int value); // 6
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int dmacman_call7_GetD_BCR(unsigned int ch); // 7
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void dmacman_call8_SetD_CHCR(unsigned int ch, int value); // 8
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int dmacman_call9_GetD_CHCR(unsigned int ch); // 9
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void dmacman_call10_SetD_TADR(unsigned int ch, int value); //10
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int dmacman_call11_GetD_TADR(unsigned int ch); //11
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void dmacman_call12_Set_4_9_A(unsigned int ch, int value); //12
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int dmacman_call13_Get_4_9_A(unsigned int ch); //13
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void dmacman_call14_SetDPCR(int value); //14
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int dmacman_call15_GetDPCR(); //15
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void dmacman_call16_SetDPCR2(int value); //16
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int dmacman_call17_GetDPCR2(); //17
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void dmacman_call18_SetDPCR3(int value); //18
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int dmacman_call19_GetDPCR3(); //19
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void dmacman_call20_SetDICR(int value); //20
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int dmacman_call21_GetDICR(); //21
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void dmacman_call22_SetDICR2(int value); //22
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int dmacman_call23_GetDICR2(); //23
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void dmacman_call24_setBF80157C(int value); //24
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int dmacman_call25_getBF80157C(); //25
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void dmacman_call26_setBF801578(int value); //26
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int dmacman_call27_getBF801578(); //27
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int dmacman_call28_SetDMA(int ch, int address, int size, int count, int dir); //28
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int dmacman_call29_SetDMA_chainedSPU_SIF0(int ch, int size, int c);//29
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int dmacman_call30_SetDMA_SIF0(int ch, int size, int c); //30
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int dmacman_call31_SetDMA_SIF1(int ch, int size); //31
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void dmacman_call32_StartTransfer(int ch); //32
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void dmacman_call33_SetVal(int ch, int value); //33
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void dmacman_call34_EnableDMAch(int ch); //34
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void dmacman_call35_DisableDMAch(int ch); //35
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//SIF2 DMA ch 2 (GPU)
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#define DMAch_SIF2_MADR (*(volatile int*)0xBF8010A0)
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#define DMAch_SIF2_BCR (*(volatile int*)0xBF8010A4)
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#define DMAch_SIF2_BCR_size (*(volatile short*)0xBF8010A4)
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#define DMAch_SIF2_BCR_count (*(volatile short*)0xBF8010A6)
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#define DMAch_SIF2_CHCR (*(volatile int*)0xBF8010A8)
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//SIF0 DMA ch 9
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#define DMAch_SIF9_MADR (*(volatile int*)0xBF801520)
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#define DMAch_SIF9_BCR (*(volatile int*)0xBF801524)
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#define DMAch_SIF9_BCR_size (*(volatile short*)0xBF801524)
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#define DMAch_SIF9_BCR_count (*(volatile short*)0xBF801526)
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#define DMAch_SIF9_CHCR (*(volatile int*)0xBF801528)
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#define DMAch_SIF9_TADR (*(volatile int*)0xBF80152C)
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//SIF1 DMA ch 10 (0xA)
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#define DMAch_SIFA_MADR (*(volatile int*)0xBF801530)
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#define DMAch_SIFA_BCR (*(volatile int*)0xBF801534)
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#define DMAch_SIFA_BCR_size (*(volatile short*)0xBF801534)
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#define DMAch_SIFA_BCR_count (*(volatile short*)0xBF801536)
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#define DMAch_SIFA_CHCR (*(volatile int*)0xBF801538)
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#define DMAch_DPCR (*(volatile int*)0xBF8010F0)
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#define DMAch_DPCR2 (*(volatile int*)0xBF801570)
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#endif//__DMACMAN_H__
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