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mgba
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2,489 Commits 36 Branches 39 Tags 69 MiB
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67 Commits

Author SHA1 Message Date
Jeffrey Pfau 051af279c9 GBA Memory: Implement game pak prefetch approximation 2015-06-22 00:27:21 -07:00
Jeffrey Pfau 910ff621b3 ARM7: Fix timing of multiplies to use N cycles 2015-06-12 03:26:50 -07:00
Jeffrey Pfau 32d1f5bbfb ARM7: Fix ARM multiply instructions when PC is a destination register 2015-05-09 13:40:58 -07:00
Jeffrey Pfau ebcb344d64 ARM7: Handle writeback for PC in addressing modes 2 and 3 2015-05-08 01:23:44 -07:00
Jeffrey Pfau 45473bf7bc ARM7: Fix cycle counting for loads 2015-03-27 21:21:17 -07:00
Jeffrey Pfau 56291e63e5 Debugger: Add support for soft breakpoints 2015-02-03 03:12:04 -08:00
Jeffrey Pfau 6d18b9aea5 GBA Memory: Simplify memory API and use fixed bus width 2015-01-10 01:20:21 -08:00
Jeffrey Pfau 3d21ce1fd0 ARM7: Fix LDM writeback to a register already written 2014-12-17 21:15:49 -08:00
Jeffrey Pfau f6a7fedb28 All: Add MPL 2.0 license and associated headers 2014-12-03 00:39:06 -08:00
Jeffrey Pfau 537480b940 Load/Store multiple functions 2014-10-21 22:35:02 -07:00
Jeffrey Pfau 823b97603a Properly account for LDR I cycles (fixes #90) 2014-07-19 00:39:51 -07:00
Jeffrey Pfau fce2fb9252 Move flags and masks into defines to avoid making enums with values that are too large 2014-07-15 23:38:44 -07:00
Jeffrey Pfau 939c349533 Slightly more accurate waitstate emulation 2014-07-13 22:21:37 -07:00
Jeffrey Pfau aefa5f0ab8 Merge branch 'decoder' 
Conflicts:
	src/debugger/cli-debugger.c
 2014-07-12 00:40:40 -07:00
Jeffrey Pfau 2921ba8842 Split ARM emitters into own file 2014-07-10 23:21:28 -07:00
Jeffrey Pfau 0f68dbc832 Redo component model/type punning 2014-04-20 00:19:55 -07:00
Jeffrey Pfau c0eb7c81f7 Remove ARMMemory and ARMBoard shims 2014-04-19 18:14:17 -07:00
Jeffrey Pfau 5d19919df2 Extract emittor macros into headers 2014-03-29 22:59:39 -07:00
Jeffrey Pfau 8e5b806cdd Have board re-read CPSR when it is modified by MSR 2014-01-27 00:21:14 -08:00
Jeffrey Pfau 52808da265 Inline CPU stepping 2014-01-21 22:36:40 -08:00
Jeffrey Pfau e7d4f3ae8a Fix MSR with immediate 2014-01-20 15:40:56 -08:00
Jeffrey Pfau 2db6d27496 Implement SWP, SWPB 2014-01-20 15:19:52 -08:00
Jeffrey Pfau fede211874 Remove checks for ARM writeback operations that fail on real hardware 2014-01-20 15:10:41 -08:00
Jeffrey Pfau a969d70de3 Handle illegal and stub opcodes separately 2014-01-18 00:39:51 -08:00
Jeffrey Pfau 915b04dded Add support for PowerPC to the memory and CPU interfaces 2013-10-26 01:53:13 -04:00
Jeffrey Pfau 3e3bb58ae5 Minor timing fixes 2013-10-08 02:10:43 -07:00
Jeffrey Pfau 25885e1e82 Invalid memory reads 2013-09-27 23:48:56 -07:00
Jeffrey Pfau 99769695d7 Fix ADCS C bit 2013-09-26 00:25:48 -07:00
Jeffrey Pfau 13a2289e25 Fix ADCS 2013-09-25 00:27:40 -07:00
Jeffrey Pfau 6b86cdf9ef LDM should force-align loads 2013-07-31 01:59:00 -07:00
Jeffrey Pfau 425056ca15 Ensure LDM does not write back incorrectly with register list overlaps 2013-07-27 03:02:52 -07:00
Jeffrey Pfau 9e578da5a1 Do register writeback in addressing mode 2 before actual load/store 2013-07-26 23:42:45 -07:00
Jeffrey Pfau 8b1eb01a96 Fix MUL, UMULL, UMLAL 2013-07-26 01:03:34 -07:00
Jeffrey Pfau a6d87bbfb9 Better cycle counting for STR 2013-05-11 18:01:16 -07:00
Jeffrey Pfau b6361cdfa9 Start LDM/STM timings 2013-05-11 17:05:57 -07:00
Jeffrey Pfau f6592b17b8 Implement MUL timings 2013-05-11 14:35:10 -07:00
Jeffrey Pfau fc7aec557b Count cycles for load/store singles 2013-05-04 23:57:12 -07:00
Jeffrey Pfau a635f4de4d Implement addressing mode 1 ASR register shift 2013-05-02 00:32:04 -07:00
Jeffrey Pfau 86c228f2e4 Implement SMLAL 2013-05-02 00:29:06 -07:00
Jeffrey Pfau 61c6b7186e Implement UMLAL 2013-05-01 23:11:00 -07:00
Jeffrey Pfau cd73c562ea Implement addressing mode 1 LSL/LSR with register 2013-05-01 23:08:22 -07:00
Jeffrey Pfau da489b90f8 Ensure shifter carry-out gets bits set right 2013-04-30 21:02:56 -07:00
Jeffrey Pfau 118c393d1b Fix addressing mode 2 register post-indexed 2013-04-30 02:43:12 -07:00
Jeffrey Pfau 337d4dc1e6 Implement addressing mode 1 ROR with register 2013-04-30 02:42:54 -07:00
Jeffrey Pfau e1963c6e60 Implement SMULL 2013-04-30 01:42:24 -07:00
Jeffrey Pfau e86f7d79fb Clean up and fix conditions for CPSR V 2013-04-28 00:19:15 -07:00
Jeffrey Pfau 19f9b72c33 Fix CPSR C being written 2013-04-28 00:06:13 -07:00
Jeffrey Pfau 682684cb6d Output MUL into the right register 2013-04-27 23:44:33 -07:00
Jeffrey Pfau 2c8786ae4c Use LE instead of GE where appropriate 2013-04-27 23:44:17 -07:00
Jeffrey Pfau 2e78381e55 Implement SWI 2013-04-27 02:56:34 -07:00