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GB MBC: Fix edge case with Pocket Cam register accesses (fixes #2557)

This commit is contained in:
Vicki Pfau 2022-06-14 15:15:11 -07:00
parent 4707368d7f
commit f7d8b77bd4
2 changed files with 6 additions and 0 deletions
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1
CHANGES
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@ -25,6 +25,7 @@ Emulation fixes:
- GB Audio: Fix APU re-enable timing glitch - GB Audio: Fix APU re-enable timing glitch
- GB I/O: Fix writing to WAVE RAM behavior (fixes mgba.io/i/1334) - GB I/O: Fix writing to WAVE RAM behavior (fixes mgba.io/i/1334)
- GB Memory: Add cursory cartridge open bus emulation (fixes mgba.io/i/2032) - GB Memory: Add cursory cartridge open bus emulation (fixes mgba.io/i/2032)
- GB MBC: Fix edge case with Pocket Cam register accesses (fixes mgba.io/i/2557)
- GB Serialize: Fix loading MBC1 states that affect bank 0 (fixes mgba.io/i/2402) - GB Serialize: Fix loading MBC1 states that affect bank 0 (fixes mgba.io/i/2402)
- GB SIO: Fix bidirectional transfer starting (fixes mgba.io/i/2290) - GB SIO: Fix bidirectional transfer starting (fixes mgba.io/i/2290)
- GB Video: Draw SGB border pieces that overlap GB graphics (fixes mgba.io/i/1339) - GB Video: Draw SGB border pieces that overlap GB graphics (fixes mgba.io/i/1339)

5
src/gb/mbc.c
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@ -1402,11 +1402,16 @@ void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
if (value < 0x10) { if (value < 0x10) {
GBMBCSwitchSramBank(gb, value); GBMBCSwitchSramBank(gb, value);
memory->mbcState.pocketCam.registersActive = false; memory->mbcState.pocketCam.registersActive = false;
memory->directSramAccess = true;
} else { } else {
memory->mbcState.pocketCam.registersActive = true; memory->mbcState.pocketCam.registersActive = true;
memory->directSramAccess = false;
} }
break; break;
case 0x5: case 0x5:
if (!memory->mbcState.pocketCam.registersActive) {
break;
}
address &= 0x7F; address &= 0x7F;
if (address == 0 && value & 1) { if (address == 0 && value & 1) {
value &= 6; // TODO: Timing value &= 6; // TODO: Timing