From f7d8b77bd47cf0d762496ad3a25aefa9ebd45ac9 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Tue, 14 Jun 2022 15:15:11 -0700 Subject: [PATCH] GB MBC: Fix edge case with Pocket Cam register accesses (fixes #2557) --- CHANGES | 1 + src/gb/mbc.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/CHANGES b/CHANGES index fed10442a..390ac425f 100644 --- a/CHANGES +++ b/CHANGES @@ -25,6 +25,7 @@ Emulation fixes: - GB Audio: Fix APU re-enable timing glitch - GB I/O: Fix writing to WAVE RAM behavior (fixes mgba.io/i/1334) - GB Memory: Add cursory cartridge open bus emulation (fixes mgba.io/i/2032) + - GB MBC: Fix edge case with Pocket Cam register accesses (fixes mgba.io/i/2557) - GB Serialize: Fix loading MBC1 states that affect bank 0 (fixes mgba.io/i/2402) - GB SIO: Fix bidirectional transfer starting (fixes mgba.io/i/2290) - GB Video: Draw SGB border pieces that overlap GB graphics (fixes mgba.io/i/1339) diff --git a/src/gb/mbc.c b/src/gb/mbc.c index 9e8724964..282891cfe 100644 --- a/src/gb/mbc.c +++ b/src/gb/mbc.c @@ -1402,11 +1402,16 @@ void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) { if (value < 0x10) { GBMBCSwitchSramBank(gb, value); memory->mbcState.pocketCam.registersActive = false; + memory->directSramAccess = true; } else { memory->mbcState.pocketCam.registersActive = true; + memory->directSramAccess = false; } break; case 0x5: + if (!memory->mbcState.pocketCam.registersActive) { + break; + } address &= 0x7F; if (address == 0 && value & 1) { value &= 6; // TODO: Timing