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Fill in immediates

This commit is contained in:
Jeffrey Pfau 2013-04-04 03:12:22 -07:00
parent 63f6f53a80
commit c07df4a337
1 changed files with 54 additions and 7 deletions
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61
src/arm.c
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@ -12,6 +12,14 @@ static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
return mode != MODE_SYSTEM && mode != MODE_USER; return mode != MODE_SYSTEM && mode != MODE_USER;
} }
static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
// TODO
}
static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
// TODO
}
static const ARMInstruction armTable[0xF000]; static const ARMInstruction armTable[0xF000];
static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) { static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
@ -159,18 +167,20 @@ inline void ARMCycle(struct ARMCore* cpu) {
DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \ DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \
DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY) DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY)
// TODO: shifter #define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S, S_BODY, BODY, POST_BODY) \ DEFINE_INSTRUCTION_ARM(NAME, \
DEFINE_INSTRUCTION_ARM(NAME ## S, \
int rd = (opcode >> 12) & 0xF; \ int rd = (opcode >> 12) & 0xF; \
int rn = (opcode >> 16) & 0xF; \ int rn = (opcode >> 16) & 0xF; \
SHIFTER(cpu, opcode); \
BODY; \ BODY; \
S_BODY; \ S_BODY; \
POST_BODY;) POST_BODY;)
#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \ #define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , , BODY, POST_BODY) \ DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S, S_BODY, BODY, POST_BODY) DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
// Begin ALU definitions // Begin ALU definitions
@ -264,6 +274,8 @@ DEFINE_INSTRUCTION_ARM(SWPB,)
DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
DEFINE_INSTRUCTION_ARM(MSR,) DEFINE_INSTRUCTION_ARM(MSR,)
DEFINE_INSTRUCTION_ARM(MRS,) DEFINE_INSTRUCTION_ARM(MRS,)
DEFINE_INSTRUCTION_ARM(MSRI,)
DEFINE_INSTRUCTION_ARM(MRSI,)
#define DECLARE_INSTRUCTION_ARM(COND, NAME) \ #define DECLARE_INSTRUCTION_ARM(COND, NAME) \
_ARMInstruction ## NAME ## COND _ARMInstruction ## NAME ## COND
@ -280,7 +292,10 @@ DEFINE_INSTRUCTION_ARM(MRS,)
DIRECTIVE, \ DIRECTIVE, \
DIRECTIVE \ DIRECTIVE \
// TODO: MUL #define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ALU) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)), \
DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I))
#define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \ #define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \ DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
DECLARE_INSTRUCTION_ARM(COND, ALU), \ DECLARE_INSTRUCTION_ARM(COND, ALU), \
@ -324,7 +339,39 @@ DEFINE_INSTRUCTION_ARM(MRS,)
DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRH, ILL, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRH, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRH, LDRSB, LDRSH), \ DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRH, LDRSB, LDRSH), \
DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRH, ILL, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRH, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRH, LDRSB, LDRSH) DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRH, LDRSB, LDRSH), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EORS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUB), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUBS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSB), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSBS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADD), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADDS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSCS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TST), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TEQ), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMP), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMN), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORR), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORRS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOV), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOVS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)
static const ARMInstruction armTable[0xF000] = { static const ARMInstruction armTable[0xF000] = {
DECLARE_COND_BLOCK(EQ), DECLARE_COND_BLOCK(EQ),