From c07df4a33749841108cf4501d69858e9f794a0c0 Mon Sep 17 00:00:00 2001
From: Jeffrey Pfau <jeffrey@endrift.com>
Date: Thu, 4 Apr 2013 03:12:22 -0700
Subject: [PATCH] Fill in immediates

---
 src/arm.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 54 insertions(+), 7 deletions(-)

diff --git a/src/arm.c b/src/arm.c
index acde87b46..0a6dcabbb 100644
--- a/src/arm.c
+++ b/src/arm.c
@@ -12,6 +12,14 @@ static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
 	return mode != MODE_SYSTEM && mode != MODE_USER;
 }
 
+static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
+	// TODO
+}
+
+static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
+	// TODO
+}
+
 static const ARMInstruction armTable[0xF000];
 
 static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
@@ -159,18 +167,20 @@ inline void ARMCycle(struct ARMCore* cpu) {
 	DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \
 	DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY)
 
-// TODO: shifter
-#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S, S_BODY, BODY, POST_BODY) \
-	DEFINE_INSTRUCTION_ARM(NAME ## S, \
+#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
+	DEFINE_INSTRUCTION_ARM(NAME, \
 		int rd = (opcode >> 12) & 0xF; \
 		int rn = (opcode >> 16) & 0xF; \
+		SHIFTER(cpu, opcode); \
 		BODY; \
 		S_BODY; \
 		POST_BODY;)
 
 #define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , , BODY, POST_BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S, S_BODY, BODY, POST_BODY)
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
 
 // Begin ALU definitions
 
@@ -264,6 +274,8 @@ DEFINE_INSTRUCTION_ARM(SWPB,)
 DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
 DEFINE_INSTRUCTION_ARM(MSR,)
 DEFINE_INSTRUCTION_ARM(MRS,)
+DEFINE_INSTRUCTION_ARM(MSRI,)
+DEFINE_INSTRUCTION_ARM(MRSI,)
 
 #define DECLARE_INSTRUCTION_ARM(COND, NAME) \
 	_ARMInstruction ## NAME ## COND
@@ -280,7 +292,10 @@ DEFINE_INSTRUCTION_ARM(MRS,)
 	DIRECTIVE, \
 	DIRECTIVE \
 
-// TODO: MUL
+#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ALU) \
+	DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)), \
+	DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I))
+
 #define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
 	DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
 	DECLARE_INSTRUCTION_ARM(COND, ALU), \
@@ -324,7 +339,39 @@ DEFINE_INSTRUCTION_ARM(MRS,)
 	DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRH, LDRSB, LDRSH), \
 	DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRH, ILL, ILL), \
-	DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRH, LDRSB, LDRSH)
+	DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EORS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUB), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUBS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSB), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSBS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADD), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADDS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADC), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADCS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBC), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBCS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSC), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSCS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TST), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TEQ), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMP), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMN), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORR), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORRS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOV), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOVS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)
 
 static const ARMInstruction armTable[0xF000] = {
 	DECLARE_COND_BLOCK(EQ),