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ARM: Fake bpkt instruction should take no cycles (fixes #2551)

This commit is contained in:
Vicki Pfau 2023-07-05 22:10:33 -07:00
parent a51cb3f921
commit afb614ad03
3 changed files with 7 additions and 2 deletions
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1
CHANGES
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@ -1,6 +1,7 @@
0.10.3: (Future) 0.10.3: (Future)
Emulation fixes: Emulation fixes:
- ARM: Remove obsolete force-alignment in `bx pc` (fixes mgba.io/i/2964) - ARM: Remove obsolete force-alignment in `bx pc` (fixes mgba.io/i/2964)
- ARM: Fake bpkt instruction should take no cycles (fixes mgba.io/i/2551)
- GB Audio: Fix channels 1/2 staying muted if restarted after long silence - GB Audio: Fix channels 1/2 staying muted if restarted after long silence
- GB Audio: Fix channel 1 restarting if sweep applies after stop (fixes mgba.io/i/2965) - GB Audio: Fix channel 1 restarting if sweep applies after stop (fixes mgba.io/i/2965)
- GB I/O: Read back proper SVBK value after writing 0 (fixes mgba.io/i/2921) - GB I/O: Read back proper SVBK value after writing 0 (fixes mgba.io/i/2921)

4
src/arm/isa-arm.c
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@ -663,7 +663,9 @@ DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
// Begin miscellaneous definitions // Begin miscellaneous definitions
DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience DEFINE_INSTRUCTION_ARM(BKPT,
cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF));
currentCycles = 0;); // Not strictly in ARMv4T, but here for convenience
DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
DEFINE_INSTRUCTION_ARM(MSR, DEFINE_INSTRUCTION_ARM(MSR,

4
src/arm/isa-thumb.c
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@ -381,7 +381,9 @@ DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
cpu->gprs[ARM_SP] = address) cpu->gprs[ARM_SP] = address)
DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL) DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);) DEFINE_INSTRUCTION_THUMB(BKPT,
cpu->irqh.bkpt16(cpu, opcode & 0xFF);
currentCycles = 0;) // Not strictly in ARMv4T, but here for convenience
DEFINE_INSTRUCTION_THUMB(B, DEFINE_INSTRUCTION_THUMB(B,
int16_t immediate = (opcode & 0x07FF) << 5; int16_t immediate = (opcode & 0x07FF) << 5;
cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4); cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);