Show s flag for ARM instructions

This commit is contained in:
Jeffrey Pfau 2014-07-12 00:13:11 -07:00
parent d245eb3f88
commit a2eec31632
4 changed files with 21 additions and 0 deletions

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@ -392,6 +392,7 @@ static const ARMDecoder _armDecoderTable[0x1000] = {
}; };
void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) { void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) {
info->execMode = MODE_ARM;
info->opcode = opcode; info->opcode = opcode;
info->branches = 0; info->branches = 0;
info->traps = 0; info->traps = 0;

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@ -312,6 +312,7 @@ static const ThumbDecoder _thumbDecoderTable[0x400] = {
}; };
void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info) { void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info) {
info->execMode = MODE_THUMB;
info->opcode = opcode; info->opcode = opcode;
info->branches = 0; info->branches = 0;
info->traps = 0; info->traps = 0;

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@ -247,6 +247,22 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
case ARM_MN_SWP: case ARM_MN_SWP:
flags = _armAccessTypeStrings[info->memory.width]; flags = _armAccessTypeStrings[info->memory.width];
break; break;
case ARM_MN_ADD:
case ARM_MN_ADC:
case ARM_MN_AND:
case ARM_MN_BIC:
case ARM_MN_EOR:
case ARM_MN_MOV:
case ARM_MN_MVN:
case ARM_MN_ORR:
case ARM_MN_RSB:
case ARM_MN_RSC:
case ARM_MN_SBC:
case ARM_MN_SUB:
if (info->affectsCPSR && info->execMode == MODE_ARM) {
flags = "s";
}
break;
default: default:
break; break;
} }

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@ -1,6 +1,8 @@
#ifndef ARM_DECODER_H #ifndef ARM_DECODER_H
#define ARM_DECODER_H #define ARM_DECODER_H
#include "arm.h"
#include <stdint.h> #include <stdint.h>
// Bit 0: a register is involved with this operand // Bit 0: a register is involved with this operand
@ -165,6 +167,7 @@ enum ARMMnemonic {
}; };
struct ARMInstructionInfo { struct ARMInstructionInfo {
enum ExecutionMode execMode;
uint32_t opcode; uint32_t opcode;
enum ARMMnemonic mnemonic; enum ARMMnemonic mnemonic;
union ARMOperand op1; union ARMOperand op1;