mgba/cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/test.sym

; this file was created with wlalink by ville helin <vhelin@iki.fi>.
; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/emulator-only/mbc1_rom_4banks.gb".

[labels]
0001:4bf3 print_load_font
0001:4c00 print_string
0001:4c0a print_a
0001:4c14 print_newline
0001:4c1f print_digit
0001:4c2c print_regs
0001:4c35 _print_sl_data0
0001:4c3b _print_sl_out0
0001:4c48 _print_sl_data1
0001:4c4e _print_sl_out1
0001:4c60 _print_sl_data2
0001:4c66 _print_sl_out2
0001:4c73 _print_sl_data3
0001:4c79 _print_sl_out3
0001:4c8b _print_sl_data4
0001:4c91 _print_sl_out4
0001:4c9e _print_sl_data5
0001:4ca4 _print_sl_out5
0001:4cb6 _print_sl_data6
0001:4cbc _print_sl_out6
0001:4cc9 _print_sl_data7
0001:4ccf _print_sl_out7
0001:4001 font
0000:c000 regs_save
0000:c000 regs_save.f
0000:c001 regs_save.a
0000:c002 regs_save.c
0000:c003 regs_save.b
0000:c004 regs_save.e
0000:c005 regs_save.d
0000:c006 regs_save.l
0000:c007 regs_save.h
0000:c008 regs_flags
0000:c009 regs_assert
0000:c009 regs_assert.f
0000:c00a regs_assert.a
0000:c00b regs_assert.c
0000:c00c regs_assert.b
0000:c00d regs_assert.e
0000:c00e regs_assert.d
0000:c00f regs_assert.l
0000:c010 regs_assert.h
0000:c011 memdump_len
0000:c012 memdump_addr
0001:47f1 memcpy
0001:47fa memset
0001:4803 clear_vram
0001:480e reset_screen
0001:481b process_results
0001:4820 _wait_ly_0
0001:4826 _wait_ly_1
0001:4842 _wait_ly_2
0001:4848 _wait_ly_3
0001:4861 _process_results_cb
0001:486c _print_sl_data8
0001:4876 _print_sl_out8
0001:4890 _print_sl_data9
0001:489b _print_sl_out9
0001:48b3 _print_sl_data10
0001:48bf _print_sl_out10
0001:48c0 dump_mem
0001:48d0 _wait_ly_4
0001:48d6 _wait_ly_5
0001:48f2 _dump_mem_line
0001:491c _check_asserts
0001:492a _print_sl_data11
0001:492d _print_sl_out11
0001:4939 _print_sl_data12
0001:493b _print_sl_out12
0001:4943 _print_sl_data13
0001:4946 _print_sl_out13
0001:4950 __check_assert_fail0
0001:495b _print_sl_data14
0001:495e _print_sl_out14
0001:4961 __check_assert_ok0
0001:4969 _print_sl_data15
0001:496e _print_sl_out15
0001:4970 __check_assert_skip0
0001:4978 _print_sl_data16
0001:4980 _print_sl_out16
0001:4980 __check_assert_out0
0001:498c _print_sl_data17
0001:498e _print_sl_out17
0001:4996 _print_sl_data18
0001:4999 _print_sl_out18
0001:49a3 __check_assert_fail1
0001:49ae _print_sl_data19
0001:49b1 _print_sl_out19
0001:49b4 __check_assert_ok1
0001:49bc _print_sl_data20
0001:49c1 _print_sl_out20
0001:49c3 __check_assert_skip1
0001:49cb _print_sl_data21
0001:49d3 _print_sl_out21
0001:49d3 __check_assert_out1
0001:49de _print_sl_data22
0001:49e1 _print_sl_out22
0001:49ed _print_sl_data23
0001:49ef _print_sl_out23
0001:49f7 _print_sl_data24
0001:49fa _print_sl_out24
0001:4a04 __check_assert_fail2
0001:4a0f _print_sl_data25
0001:4a12 _print_sl_out25
0001:4a15 __check_assert_ok2
0001:4a1d _print_sl_data26
0001:4a22 _print_sl_out26
0001:4a24 __check_assert_skip2
0001:4a2c _print_sl_data27
0001:4a34 _print_sl_out27
0001:4a34 __check_assert_out2
0001:4a40 _print_sl_data28
0001:4a42 _print_sl_out28
0001:4a4a _print_sl_data29
0001:4a4d _print_sl_out29
0001:4a57 __check_assert_fail3
0001:4a62 _print_sl_data30
0001:4a65 _print_sl_out30
0001:4a68 __check_assert_ok3
0001:4a70 _print_sl_data31
0001:4a75 _print_sl_out31
0001:4a77 __check_assert_skip3
0001:4a7f _print_sl_data32
0001:4a87 _print_sl_out32
0001:4a87 __check_assert_out3
0001:4a92 _print_sl_data33
0001:4a95 _print_sl_out33
0001:4aa1 _print_sl_data34
0001:4aa3 _print_sl_out34
0001:4aab _print_sl_data35
0001:4aae _print_sl_out35
0001:4ab8 __check_assert_fail4
0001:4ac3 _print_sl_data36
0001:4ac6 _print_sl_out36
0001:4ac9 __check_assert_ok4
0001:4ad1 _print_sl_data37
0001:4ad6 _print_sl_out37
0001:4ad8 __check_assert_skip4
0001:4ae0 _print_sl_data38
0001:4ae8 _print_sl_out38
0001:4ae8 __check_assert_out4
0001:4af4 _print_sl_data39
0001:4af6 _print_sl_out39
0001:4afe _print_sl_data40
0001:4b01 _print_sl_out40
0001:4b0b __check_assert_fail5
0001:4b16 _print_sl_data41
0001:4b19 _print_sl_out41
0001:4b1c __check_assert_ok5
0001:4b24 _print_sl_data42
0001:4b29 _print_sl_out42
0001:4b2b __check_assert_skip5
0001:4b33 _print_sl_data43
0001:4b3b _print_sl_out43
0001:4b3b __check_assert_out5
0001:4b46 _print_sl_data44
0001:4b49 _print_sl_out44
0001:4b55 _print_sl_data45
0001:4b57 _print_sl_out45
0001:4b5f _print_sl_data46
0001:4b62 _print_sl_out46
0001:4b6c __check_assert_fail6
0001:4b77 _print_sl_data47
0001:4b7a _print_sl_out47
0001:4b7d __check_assert_ok6
0001:4b85 _print_sl_data48
0001:4b8a _print_sl_out48
0001:4b8c __check_assert_skip6
0001:4b94 _print_sl_data49
0001:4b9c _print_sl_out49
0001:4b9c __check_assert_out6
0001:4ba8 _print_sl_data50
0001:4baa _print_sl_out50
0001:4bb2 _print_sl_data51
0001:4bb5 _print_sl_out51
0001:4bbf __check_assert_fail7
0001:4bca _print_sl_data52
0001:4bcd _print_sl_out52
0001:4bd0 __check_assert_ok7
0001:4bd8 _print_sl_data53
0001:4bdd _print_sl_out53
0001:4bdf __check_assert_skip7
0001:4be7 _print_sl_data54
0001:4bef _print_sl_out54
0001:4bef __check_assert_out7
0000:01c8 _wait_ly_6
0000:01ce _wait_ly_7
0000:01ea _wait_ly_8
0000:01f0 _wait_ly_9
0000:0209 _test_ok_cb_0
0000:0211 _print_sl_data55
0000:0219 _print_sl_out55
0000:021c switch_bank
0000:0225 test_mbc
0000:0236 _wait_ly_10
0000:023c _wait_ly_11
0000:0258 _wait_ly_12
0000:025e _wait_ly_13
0000:0277 _test_failure_cb_0
0000:027f _print_sl_data56
0000:028b _print_sl_out56