733 lines
16 KiB
C++
733 lines
16 KiB
C++
/*
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Copyright 2016-2017 StapleButter
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "NDS.h"
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#include "GPU.h"
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namespace GPU
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{
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#define LINE_CYCLES (355*6)
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#define HBLANK_CYCLES (256*6)
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#define FRAME_CYCLES (LINE_CYCLES * 263)
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u16 VCount;
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u16 DispStat[2], VMatch[2];
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u8 Palette[2*1024];
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u8 OAM[2*1024];
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u8 VRAM_A[128*1024];
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u8 VRAM_B[128*1024];
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u8 VRAM_C[128*1024];
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u8 VRAM_D[128*1024];
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u8 VRAM_E[ 64*1024];
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u8 VRAM_F[ 16*1024];
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u8 VRAM_G[ 16*1024];
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u8 VRAM_H[ 32*1024];
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u8 VRAM_I[ 16*1024];
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u8* VRAM[9] = {VRAM_A, VRAM_B, VRAM_C, VRAM_D, VRAM_E, VRAM_F, VRAM_G, VRAM_H, VRAM_I};
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u8 VRAMCNT[9];
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u8 VRAMSTAT;
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//u32 VRAM_Base[9];
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//u32 VRAM_Mask[9];
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u32 VRAMMap_LCDC;
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u32 VRAMMap_ABG[0x20];
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u32 VRAMMap_AOBJ[0x10];
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u32 VRAMMap_BBG[0x8];
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u32 VRAMMap_BOBJ[0x8];
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u32 VRAMMap_ABGExtPal[4];
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u32 VRAMMap_AOBJExtPal;
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u32 VRAMMap_BBGExtPal[4];
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u32 VRAMMap_BOBJExtPal;
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u32 VRAMMap_Texture[4];
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u32 VRAMMap_TexPal[6];
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u32 VRAMMap_ARM7[2];
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/*u8* VRAM_ABG[128];
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u8* VRAM_AOBJ[128];
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u8* VRAM_BBG[128];
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u8* VRAM_BOBJ[128];
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u8* VRAM_LCD[128];*/
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/*u8* VRAM_ARM7[2];
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u8* VRAM_ABGExtPal[4];
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u8* VRAM_AOBJExtPal;
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u8* VRAM_BBGExtPal[4];
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u8* VRAM_BOBJExtPal;*/
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u32 Framebuffer[256*192*2];
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GPU2D* GPU2D_A;
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GPU2D* GPU2D_B;
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bool Init()
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{
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GPU2D_A = new GPU2D(0);
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GPU2D_B = new GPU2D(1);
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if (!GPU3D::Init()) return false;
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return true;
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}
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void DeInit()
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{
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delete GPU2D_A;
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delete GPU2D_B;
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GPU3D::DeInit();
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}
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void Reset()
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{
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VCount = 0;
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DispStat[0] = 0;
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DispStat[1] = 0;
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VMatch[0] = 0;
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VMatch[1] = 0;
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memset(Palette, 0, 2*1024);
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memset(OAM, 0, 2*1024);
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memset(VRAM_A, 0, 128*1024);
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memset(VRAM_B, 0, 128*1024);
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memset(VRAM_C, 0, 128*1024);
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memset(VRAM_D, 0, 128*1024);
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memset(VRAM_E, 0, 64*1024);
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memset(VRAM_F, 0, 16*1024);
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memset(VRAM_G, 0, 16*1024);
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memset(VRAM_H, 0, 32*1024);
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memset(VRAM_I, 0, 16*1024);
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memset(VRAMCNT, 0, 9);
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VRAMSTAT = 0;
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VRAMMap_LCDC = 0;
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memset(VRAMMap_ABG, 0, sizeof(VRAMMap_ABG));
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memset(VRAMMap_AOBJ, 0, sizeof(VRAMMap_AOBJ));
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memset(VRAMMap_BBG, 0, sizeof(VRAMMap_BBG));
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memset(VRAMMap_BOBJ, 0, sizeof(VRAMMap_BOBJ));
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memset(VRAMMap_ABGExtPal, 0, sizeof(VRAMMap_ABGExtPal));
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VRAMMap_AOBJExtPal = 0;
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memset(VRAMMap_BBGExtPal, 0, sizeof(VRAMMap_BBGExtPal));
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VRAMMap_BOBJExtPal = 0;
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memset(VRAMMap_Texture, 0, sizeof(VRAMMap_Texture));
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memset(VRAMMap_TexPal, 0, sizeof(VRAMMap_TexPal));
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VRAMMap_ARM7[0] = 0;
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VRAMMap_ARM7[1] = 0;
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//memset(VRAM_Base, 0, sizeof(VRAM_Base));
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//memset(VRAM_Mask, 0, sizeof(VRAM_Mask));
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/*memset(VRAM_ABG, 0, sizeof(u8*)*128);
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memset(VRAM_AOBJ, 0, sizeof(u8*)*128);
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memset(VRAM_BBG, 0, sizeof(u8*)*128);
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memset(VRAM_BOBJ, 0, sizeof(u8*)*128);
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memset(VRAM_LCD, 0, sizeof(u8*)*128);*/
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/*memset(VRAM_ARM7, 0, sizeof(u8*)*2);
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memset(VRAM_ABGExtPal, 0, sizeof(u8*)*4);
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VRAM_AOBJExtPal = NULL;
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memset(VRAM_BBGExtPal, 0, sizeof(u8*)*4);
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VRAM_BOBJExtPal = NULL;*/
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for (int i = 0; i < 256*192*2; i++)
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{
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Framebuffer[i] = 0xFFFFFFFF;
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}
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GPU2D_A->Reset();
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GPU2D_B->Reset();
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GPU3D::Reset();
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GPU2D_A->SetFramebuffer(&Framebuffer[256*192]);
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GPU2D_B->SetFramebuffer(&Framebuffer[256*0]);
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}
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// VRAM mapping notes
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//
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// mirroring:
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// unmapped range reads zero
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// LCD is mirrored every 0x100000 bytes, the gap between each mirror reads zero
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// ABG:
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// bank A,B,C,D,E mirror every 0x80000 bytes
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// bank F,G mirror at base+0x8000, mirror every 0x80000 bytes
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// AOBJ:
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// bank A,B,E mirror every 0x40000 bytes
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// bank F,G mirror at base+0x8000, mirror every 0x40000 bytes
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// BBG:
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// bank C mirrors every 0x20000 bytes
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// bank H mirrors every 0x10000 bytes
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// bank I mirrors at base+0x4000, mirrors every 0x10000 bytes
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// BOBJ:
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// bank D mirrors every 0x20000 bytes
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// bank I mirrors every 0x4000 bytes
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//
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// untested:
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// ARM7 (TODO)
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// extended palette (mirroring doesn't apply)
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// texture/texpal (does mirroring apply?)
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// -> trying to use extpal/texture/texpal with no VRAM mapped.
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// would likely read all black, but has to be tested.
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//
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// overlap:
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// when reading: values are read from each bank and ORed together
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// when writing: value is written to each bank
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#define MAP_RANGE(map, base, n) for (int i = 0; i < n; i++) map[(base)+i] |= bankmask;
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#define UNMAP_RANGE(map, base, n) for (int i = 0; i < n; i++) map[(base)+i] &= ~bankmask;
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void MapVRAM_AB(u32 bank, u8 cnt)
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{
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u8 oldcnt = VRAMCNT[bank];
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VRAMCNT[bank] = cnt;
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if (oldcnt == cnt) return;
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u8 oldofs = (oldcnt >> 3) & 0x3;
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u8 ofs = (cnt >> 3) & 0x3;
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u32 bankmask = 1 << bank;
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if (oldcnt & (1<<7))
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{
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switch (oldcnt & 0x3)
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{
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case 0: // LCDC
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VRAMMap_LCDC &= ~bankmask;
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break;
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case 1: // ABG
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UNMAP_RANGE(VRAMMap_ABG, oldofs<<3, 8);
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break;
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case 2: // AOBJ
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oldofs &= 0x1;
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UNMAP_RANGE(VRAMMap_AOBJ, oldofs<<3, 8);
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break;
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case 3: // texture
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VRAMMap_Texture[oldofs] &= ~bankmask;
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break;
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}
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}
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if (cnt & (1<<7))
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{
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switch (cnt & 0x3)
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{
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case 0: // LCDC
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VRAMMap_LCDC |= bankmask;
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break;
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case 1: // ABG
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MAP_RANGE(VRAMMap_ABG, ofs<<3, 8);
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break;
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case 2: // AOBJ
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ofs &= 0x1;
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MAP_RANGE(VRAMMap_AOBJ, ofs<<3, 8);
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break;
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case 3: // texture
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VRAMMap_Texture[ofs] |= bankmask;
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break;
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}
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}
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}
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void MapVRAM_CD(u32 bank, u8 cnt)
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{
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u8 oldcnt = VRAMCNT[bank];
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VRAMCNT[bank] = cnt;
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VRAMSTAT &= ~(1 << (bank-2));
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if (oldcnt == cnt) return;
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u8 oldofs = (oldcnt >> 3) & 0x7;
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u8 ofs = (cnt >> 3) & 0x7;
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u32 bankmask = 1 << bank;
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if (oldcnt & (1<<7))
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{
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switch (oldcnt & 0x7)
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{
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case 0: // LCDC
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VRAMMap_LCDC &= ~bankmask;
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break;
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case 1: // ABG
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UNMAP_RANGE(VRAMMap_ABG, oldofs<<3, 8);
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break;
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case 2: // ARM7 VRAM
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oldofs &= 0x1;
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VRAMMap_ARM7[oldofs] &= ~bankmask;
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break;
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case 3: // texture
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VRAMMap_Texture[oldofs] &= ~bankmask;
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break;
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case 4: // BBG/BOBJ
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if (bank == 2)
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{
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UNMAP_RANGE(VRAMMap_BBG, 0, 8);
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}
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else
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{
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UNMAP_RANGE(VRAMMap_BOBJ, 0, 8);
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}
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break;
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}
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}
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if (cnt & (1<<7))
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{
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switch (cnt & 0x7)
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{
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case 0: // LCDC
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VRAMMap_LCDC |= bankmask;
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break;
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case 1: // ABG
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MAP_RANGE(VRAMMap_ABG, ofs<<3, 8);
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break;
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case 2: // ARM7 VRAM
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ofs &= 0x1;
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VRAMMap_ARM7[ofs] |= bankmask;
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VRAMSTAT |= (1 << (bank-2));
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break;
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case 3: // texture
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VRAMMap_Texture[ofs] |= bankmask;
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break;
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case 4: // BBG/BOBJ
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if (bank == 2)
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{
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MAP_RANGE(VRAMMap_BBG, 0, 8);
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}
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else
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{
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MAP_RANGE(VRAMMap_BOBJ, 0, 8);
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}
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break;
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}
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}
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}
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void MapVRAM_E(u32 bank, u8 cnt)
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{
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u8 oldcnt = VRAMCNT[bank];
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VRAMCNT[bank] = cnt;
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if (oldcnt == cnt) return;
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u32 bankmask = 1 << bank;
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if (oldcnt & (1<<7))
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{
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switch (oldcnt & 0x7)
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{
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case 0: // LCDC
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VRAMMap_LCDC &= ~bankmask;
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break;
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case 1: // ABG
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UNMAP_RANGE(VRAMMap_ABG, 0, 4);
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break;
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case 2: // AOBJ
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UNMAP_RANGE(VRAMMap_AOBJ, 0, 4);
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break;
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case 3: // texture palette
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UNMAP_RANGE(VRAMMap_TexPal, 0, 4);
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break;
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case 4: // ABG ext palette
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UNMAP_RANGE(VRAMMap_ABGExtPal, 0, 4);
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GPU2D_A->BGExtPalDirty(0);
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GPU2D_A->BGExtPalDirty(2);
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break;
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}
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}
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if (cnt & (1<<7))
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{
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switch (cnt & 0x7)
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{
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case 0: // LCDC
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VRAMMap_LCDC |= bankmask;
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break;
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case 1: // ABG
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MAP_RANGE(VRAMMap_ABG, 0, 4);
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break;
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case 2: // AOBJ
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MAP_RANGE(VRAMMap_AOBJ, 0, 4);
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break;
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case 3: // texture palette
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MAP_RANGE(VRAMMap_TexPal, 0, 4);
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break;
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case 4: // ABG ext palette
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MAP_RANGE(VRAMMap_ABGExtPal, 0, 4);
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GPU2D_A->BGExtPalDirty(0);
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GPU2D_A->BGExtPalDirty(2);
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break;
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}
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}
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}
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void MapVRAM_FG(u32 bank, u8 cnt)
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{
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u8 oldcnt = VRAMCNT[bank];
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VRAMCNT[bank] = cnt;
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if (oldcnt == cnt) return;
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u8 oldofs = (oldcnt >> 3) & 0x7;
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u8 ofs = (cnt >> 3) & 0x7;
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u32 bankmask = 1 << bank;
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if (oldcnt & (1<<7))
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{
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switch (oldcnt & 0x7)
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{
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case 0: // LCDC
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VRAMMap_LCDC &= ~bankmask;
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break;
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case 1: // ABG
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VRAMMap_ABG[(oldofs & 0x1) + ((oldofs & 0x2) << 1)] &= ~bankmask;
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VRAMMap_ABG[(oldofs & 0x1) + ((oldofs & 0x2) << 1) + 2] &= ~bankmask;
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break;
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case 2: // AOBJ
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VRAMMap_AOBJ[(oldofs & 0x1) + ((oldofs & 0x2) << 1)] &= ~bankmask;
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VRAMMap_AOBJ[(oldofs & 0x1) + ((oldofs & 0x2) << 1) + 2] &= ~bankmask;
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break;
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case 3: // texture palette
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VRAMMap_TexPal[(oldofs & 0x1) + ((oldofs & 0x2) << 1)] &= ~bankmask;
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break;
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case 4: // ABG ext palette
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VRAMMap_ABGExtPal[((oldofs & 0x1) << 1)] &= ~bankmask;
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VRAMMap_ABGExtPal[((oldofs & 0x1) << 1) + 1] &= ~bankmask;
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GPU2D_A->BGExtPalDirty(0);
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GPU2D_A->BGExtPalDirty(2);
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break;
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case 5: // AOBJ ext palette
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VRAMMap_AOBJExtPal &= ~bankmask;
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GPU2D_A->OBJExtPalDirty();
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break;
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}
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}
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if (cnt & (1<<7))
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{
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switch (cnt & 0x7)
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{
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case 0: // LCDC
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VRAMMap_LCDC |= bankmask;
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break;
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case 1: // ABG
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VRAMMap_ABG[(ofs & 0x1) + ((ofs & 0x2) << 1)] |= bankmask;
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VRAMMap_ABG[(ofs & 0x1) + ((ofs & 0x2) << 1) + 2] |= bankmask;
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break;
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case 2: // AOBJ
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VRAMMap_AOBJ[(ofs & 0x1) + ((ofs & 0x2) << 1)] |= bankmask;
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VRAMMap_AOBJ[(ofs & 0x1) + ((ofs & 0x2) << 1) + 2] |= bankmask;
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break;
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case 3: // texture palette
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VRAMMap_TexPal[(ofs & 0x1) + ((ofs & 0x2) << 1)] |= bankmask;
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break;
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case 4: // ABG ext palette
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VRAMMap_ABGExtPal[((ofs & 0x1) << 1)] |= bankmask;
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VRAMMap_ABGExtPal[((ofs & 0x1) << 1) + 1] |= bankmask;
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GPU2D_A->BGExtPalDirty(0);
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GPU2D_A->BGExtPalDirty(2);
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break;
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case 5: // AOBJ ext palette
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VRAMMap_AOBJExtPal |= bankmask;
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GPU2D_A->OBJExtPalDirty();
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break;
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}
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}
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}
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void MapVRAM_H(u32 bank, u8 cnt)
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{
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u8 oldcnt = VRAMCNT[bank];
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VRAMCNT[bank] = cnt;
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if (oldcnt == cnt) return;
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u32 bankmask = 1 << bank;
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if (oldcnt & (1<<7))
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{
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switch (oldcnt & 0x3)
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{
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case 0: // LCDC
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VRAMMap_LCDC &= ~bankmask;
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break;
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case 1: // BBG
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VRAMMap_BBG[0] &= ~bankmask;
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VRAMMap_BBG[1] &= ~bankmask;
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VRAMMap_BBG[4] &= ~bankmask;
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VRAMMap_BBG[5] &= ~bankmask;
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break;
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case 2: // BBG ext palette
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UNMAP_RANGE(VRAMMap_BBGExtPal, 0, 4);
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GPU2D_B->BGExtPalDirty(0);
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GPU2D_B->BGExtPalDirty(2);
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break;
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}
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}
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|
if (cnt & (1<<7))
|
|
{
|
|
switch (cnt & 0x3)
|
|
{
|
|
case 0: // LCDC
|
|
VRAMMap_LCDC |= bankmask;
|
|
break;
|
|
|
|
case 1: // BBG
|
|
VRAMMap_BBG[0] |= bankmask;
|
|
VRAMMap_BBG[1] |= bankmask;
|
|
VRAMMap_BBG[4] |= bankmask;
|
|
VRAMMap_BBG[5] |= bankmask;
|
|
break;
|
|
|
|
case 2: // BBG ext palette
|
|
MAP_RANGE(VRAMMap_BBGExtPal, 0, 4);
|
|
GPU2D_B->BGExtPalDirty(0);
|
|
GPU2D_B->BGExtPalDirty(2);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void MapVRAM_I(u32 bank, u8 cnt)
|
|
{
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
u32 bankmask = 1 << bank;
|
|
|
|
if (oldcnt & (1<<7))
|
|
{
|
|
switch (oldcnt & 0x3)
|
|
{
|
|
case 0: // LCDC
|
|
VRAMMap_LCDC &= ~bankmask;
|
|
break;
|
|
|
|
case 1: // BBG
|
|
VRAMMap_BBG[2] &= ~bankmask;
|
|
VRAMMap_BBG[3] &= ~bankmask;
|
|
VRAMMap_BBG[6] &= ~bankmask;
|
|
VRAMMap_BBG[7] &= ~bankmask;
|
|
break;
|
|
|
|
case 2: // BOBJ
|
|
UNMAP_RANGE(VRAMMap_BOBJ, 0, 8);
|
|
break;
|
|
|
|
case 3: // BOBJ ext palette
|
|
VRAMMap_BOBJExtPal &= ~bankmask;
|
|
GPU2D_B->OBJExtPalDirty();
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (cnt & (1<<7))
|
|
{
|
|
switch (cnt & 0x3)
|
|
{
|
|
case 0: // LCDC
|
|
VRAMMap_LCDC |= bankmask;
|
|
break;
|
|
|
|
case 1: // BBG
|
|
VRAMMap_BBG[2] |= bankmask;
|
|
VRAMMap_BBG[3] |= bankmask;
|
|
VRAMMap_BBG[6] |= bankmask;
|
|
VRAMMap_BBG[7] |= bankmask;
|
|
break;
|
|
|
|
case 2: // BOBJ
|
|
MAP_RANGE(VRAMMap_BOBJ, 0, 8);
|
|
break;
|
|
|
|
case 3: // BOBJ ext palette
|
|
VRAMMap_BOBJExtPal |= bankmask;
|
|
GPU2D_B->OBJExtPalDirty();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void DisplaySwap(u32 val)
|
|
{
|
|
if (val)
|
|
{
|
|
GPU2D_A->SetFramebuffer(&Framebuffer[256*0]);
|
|
GPU2D_B->SetFramebuffer(&Framebuffer[256*192]);
|
|
}
|
|
else
|
|
{
|
|
GPU2D_A->SetFramebuffer(&Framebuffer[256*192]);
|
|
GPU2D_B->SetFramebuffer(&Framebuffer[256*0]);
|
|
}
|
|
}
|
|
|
|
|
|
void StartFrame()
|
|
{
|
|
StartScanline(0);
|
|
}
|
|
|
|
void StartHBlank(u32 line)
|
|
{
|
|
DispStat[0] |= (1<<1);
|
|
DispStat[1] |= (1<<1);
|
|
|
|
if (line < 192) NDS::CheckDMAs(0, 0x02);
|
|
|
|
if (DispStat[0] & (1<<4)) NDS::TriggerIRQ(0, NDS::IRQ_HBlank);
|
|
if (DispStat[1] & (1<<4)) NDS::TriggerIRQ(1, NDS::IRQ_HBlank);
|
|
|
|
if (line < 262)
|
|
NDS::ScheduleEvent(NDS::Event_LCD, true, (LINE_CYCLES - HBLANK_CYCLES), StartScanline, line+1);
|
|
}
|
|
|
|
void StartScanline(u32 line)
|
|
{
|
|
VCount = line;
|
|
|
|
DispStat[0] &= ~(1<<1);
|
|
DispStat[1] &= ~(1<<1);
|
|
|
|
if (line == VMatch[0])
|
|
{
|
|
DispStat[0] |= (1<<2);
|
|
|
|
if (DispStat[0] & (1<<5)) NDS::TriggerIRQ(0, NDS::IRQ_VCount);
|
|
}
|
|
else
|
|
DispStat[0] &= ~(1<<2);
|
|
|
|
if (line == VMatch[1])
|
|
{
|
|
DispStat[1] |= (1<<2);
|
|
|
|
if (DispStat[1] & (1<<5)) NDS::TriggerIRQ(1, NDS::IRQ_VCount);
|
|
}
|
|
else
|
|
DispStat[1] &= ~(1<<2);
|
|
|
|
if (line < 192)
|
|
{
|
|
// draw
|
|
GPU2D_A->DrawScanline(line);
|
|
GPU2D_B->DrawScanline(line);
|
|
|
|
//NDS::ScheduleEvent(LINE_CYCLES, StartScanline, line+1);
|
|
}
|
|
else if (line == 262)
|
|
{
|
|
// frame end
|
|
|
|
DispStat[0] &= ~(1<<0);
|
|
DispStat[1] &= ~(1<<0);
|
|
}
|
|
else
|
|
{
|
|
if (line == 192)
|
|
{
|
|
// VBlank
|
|
DispStat[0] |= (1<<0);
|
|
DispStat[1] |= (1<<0);
|
|
|
|
NDS::CheckDMAs(0, 0x01);
|
|
NDS::CheckDMAs(1, 0x11);
|
|
|
|
if (DispStat[0] & (1<<3)) NDS::TriggerIRQ(0, NDS::IRQ_VBlank);
|
|
if (DispStat[1] & (1<<3)) NDS::TriggerIRQ(1, NDS::IRQ_VBlank);
|
|
|
|
GPU2D_A->VBlank();
|
|
GPU2D_B->VBlank();
|
|
GPU3D::VBlank();
|
|
}
|
|
|
|
//NDS::ScheduleEvent(LINE_CYCLES, StartScanline, line+1);
|
|
//NDS::ScheduleEvent(NDS::Event_LCD, true, LINE_CYCLES, StartScanline, line+1);
|
|
}
|
|
|
|
NDS::ScheduleEvent(NDS::Event_LCD, true, HBLANK_CYCLES, StartHBlank, line);
|
|
}
|
|
|
|
|
|
void SetDispStat(u32 cpu, u16 val)
|
|
{
|
|
val &= 0xFFB8;
|
|
DispStat[cpu] &= 0x0047;
|
|
DispStat[cpu] |= val;
|
|
|
|
VMatch[cpu] = (val >> 8) | ((val & 0x80) << 1);
|
|
}
|
|
|
|
}
|