Jaklyy
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541e1e6388
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proper timings for ldr/str
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2024-06-25 09:08:11 -04:00 |
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Jaklyy
|
dbe00e72dd
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improve stm timings
need to verify if they apply to all store instructions
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2024-06-24 22:50:04 -04:00 |
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Jaklyy
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109bbed3d0
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improve ldm timings
I believe this also applies to other loads as well, but currently untested.
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2024-06-24 20:22:38 -04:00 |
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Jaklyy
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3583d8222f
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disable interlock emulation, needs more research
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2024-06-24 16:17:04 -04:00 |
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Jaklyy
|
f1b71fe5a9
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implement configurable vram bus width
not implemented for direct boot
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2024-06-24 16:15:04 -04:00 |
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Jaklyy
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e6ba4075b9
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correct interlocked reg for umlal
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2024-06-18 11:12:05 -04:00 |
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Jaklyy
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c5258d6377
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verify interlocks for alu and load/store
remove some checks for interlock that im pretty sure can't trigger
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2024-06-17 18:07:53 -04:00 |
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Jaklyy
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a9e2c7e047
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implement two regs i missed
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2024-06-16 23:24:20 -04:00 |
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Jaklyy
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f00f1f6ca4
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im smart
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2024-06-16 20:50:42 -04:00 |
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Jaklyy
|
5b37ca70d1
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implement correct/guess interlocks for remaining instructions
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2024-06-16 20:47:01 -04:00 |
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Jaklyy
|
debaaa0425
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fix performance regression for disabling interlock emulation path
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2024-06-15 21:16:12 -04:00 |
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Jaklyy
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449557624d
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don't do interlocks for the arm7
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2024-06-15 18:37:31 -04:00 |
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Jaklyy
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a973c0bf5b
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initial implementation of interlock cycles
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2024-06-15 16:07:36 -04:00 |
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Jaklyy
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aa1217af0a
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track interlock cycles for the ALU
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2024-06-14 11:47:42 -04:00 |
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Jaklyy
|
5a174a2ce3
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track interlock cycles for load instructions
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2024-06-14 00:51:55 -04:00 |
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Jaklyy
|
42218106b0
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verify writable msr bits
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2024-06-11 10:30:30 -04:00 |
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Jaklyy
|
048b0b8878
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swp/swpb jumps work on the arm 7?
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2024-06-10 18:03:56 -04:00 |
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Jaklyy
|
3ddccde5b9
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verified
also remove no longer needed variable
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2024-06-10 13:23:18 -04:00 |
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Jaklyy
|
ca04710deb
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ldrd is just ldm
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2024-06-09 22:31:10 -04:00 |
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Jaklyy
|
ae0824fdd3
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it all makes sense now...
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2024-06-09 19:10:43 -04:00 |
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Jaklyy
|
b90d5c2320
|
what the actual F*** is going on
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2024-06-09 12:18:31 -04:00 |
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Jaklyy
|
be60c68aeb
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more weirdness
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2024-06-09 07:25:42 -04:00 |
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Jaklyy
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b846c6f100
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remove out of date comments
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2024-06-08 22:17:07 -04:00 |
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Jaklyy
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849d4e51ac
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imma be real, i have no idea what is going on here
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2024-06-08 22:12:44 -04:00 |
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Jaklyy
|
659763f903
|
clarification
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2024-06-08 16:15:02 -04:00 |
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Jaklyy
|
3699768ac9
|
most cpsr bits can't actually be updated (or at least can't be read?)
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2024-06-08 14:01:54 -04:00 |
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Jaklyy
|
5f97dfc1ab
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fix bits fixed to 0 for pu region sizing being set
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2024-06-08 10:53:22 -04:00 |
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Jaklyy
|
8191f92bb6
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mcr is also affected
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2024-06-08 10:42:19 -04:00 |
|
Jaklyy
|
0c887202e7
|
fix some more instructions?
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2024-06-08 10:40:23 -04:00 |
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Jaklyy
|
73507621f5
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idk why it took me two tries to get these instructions to work properly
|
2024-06-07 23:50:31 -04:00 |
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Jaklyy
|
2b0ed459e1
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fully implement r15 stores being +12 of addr
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2024-06-07 23:46:49 -04:00 |
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Jaklyy
|
bd3611b51d
|
unaligned registers with strd/ldrd raise an exception
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2024-06-07 20:43:02 -04:00 |
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Jaklyy
|
8bc7e4591c
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thumb ldmia/pop data aborts
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2024-06-06 19:05:28 -04:00 |
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Jaklyy
|
d6cd189455
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rework data abort handling for ldm/stm; implement thumb stmia+push
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2024-06-06 18:58:43 -04:00 |
|
Jaklyy
|
13ae96b4e3
|
simple thumb instructions (untested but probably right)
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2024-06-05 14:32:12 -04:00 |
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Jaklyy
|
7c3108e20f
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handle swp instruction aborts
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2024-06-05 14:31:44 -04:00 |
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Jaklyy
|
1871c48849
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fix double data aborts with strd
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2024-06-05 10:28:51 -04:00 |
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Jaklyy
|
317a8c61e5
|
data abort handling for (almost) all (arm) instructions
full list: strb, ldrb, strh, ldrd, strd, ldrh, ldrsb, ldrsh
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2024-06-05 00:14:14 -04:00 |
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Jaklyy
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1e8194e367
|
fix ldr and str
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2024-06-04 19:06:54 -04:00 |
|
Jaklyy
|
c2a57b79a0
|
fix stmd(a/b) writeback
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2024-06-02 22:41:01 -04:00 |
|
Jaklyy
|
5e760a1536
|
slightly cleaner code
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2024-06-02 19:34:29 -04:00 |
|
Jaklyy
|
b5c1ee33fb
|
implement stm
|
2024-06-02 10:33:29 -04:00 |
|
Jaklyy
|
63d4b78733
|
improve implementation
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2024-06-02 10:13:50 -04:00 |
|
Jaklyy
|
960f063eaa
|
improve data aborts for ldm
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2024-06-02 00:11:01 -04:00 |
|
Jaklyy
|
065573f316
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fix writebacks overwriting registers swapped with spsr
fixes gbarunner3
|
2024-05-31 18:09:45 -04:00 |
|
Nadia Holmquist Pedersen
|
a72b79a55a
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that needs to be public actually
|
2024-05-15 19:43:34 +02:00 |
|
Nadia Holmquist Pedersen
|
cfc49eb286
|
Revert slirp dynamic/static check, and make it not use dllimport/export
when building statically
|
2024-05-15 19:37:14 +02:00 |
|
Nadia Holmquist Pedersen
|
d21bc64cb3
|
MinGW build portability fixes
AKA you can build melonDS for Windows on Fedora now
|
2024-05-15 18:57:49 +02:00 |
|
Nadia Holmquist Pedersen
|
a2406e3c0e
|
Vendored libslirp (#2045)
Add vendored libslirp into the repo with a shim to remove its dependency on glib.
|
2024-05-15 18:00:55 +02:00 |
|
Nadia Holmquist Pedersen
|
747f50de98
|
Refactor how CCache is set up
* Use RULE_LAUNCH_COMPILE property as you're apparently supposed to
* Detect if compiler is already ccache to prevent build failure
|
2024-05-15 10:55:10 +02:00 |