05c153e9ab
Merge branch 'interpreter-fixes' into less-ambitious-timing-rework
2024-10-15 20:23:14 -04:00
5f003eb967
fix builds with jit disabled
2024-10-15 20:23:03 -04:00
026719acef
improve timing model
2024-10-14 20:15:03 -04:00
801f43dfc5
reimplement codemem
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i dont feel like i actually had a good reason for disabling this...
2024-10-13 20:06:39 -04:00
e25dca0030
writing to the write buffer has a 1 cycle delay before it can be done again
2024-10-10 03:14:01 -04:00
6e30cf3bfb
functional write buffer prototype
2024-10-09 17:46:50 -04:00
c62f0f1244
Merge branch 'interpreter-fixes' into less-ambitious-timing-rework
2024-09-29 22:42:40 -04:00
a11208ec6d
oops
2024-09-24 21:02:17 -04:00
3065141ed7
probably not faster
2024-09-24 17:04:52 -04:00
e1d4fbef75
i can't reproduce this anymore
2024-09-24 09:47:32 -04:00
7b0d71dbbe
Revert T bit changing support for arm7
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i cannot comprehend what is happening currently
2024-09-22 19:57:33 -04:00
8d451dff48
misaligned pc..........
2024-09-20 23:47:40 -04:00
157e9c5b04
reimplement changing t bit with arm7
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kinda slow though?
2024-09-20 13:37:58 -04:00
45f87a1c8d
prevent t bit changes without pipeline flush on arm7
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idk what's happening fully and its gonna be slow to emulate most likely
we'll figure this out later
2024-09-19 21:02:54 -04:00
6ebabde392
implement changing thumb bit. and bkpt ig
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probably wrong
2024-09-19 04:37:01 -04:00
f2a02abd16
Merge branch 'interpreter-fixes' into less-ambitious-timing-rework
2024-09-13 13:51:12 -04:00
c5ac682f04
improve data abort handling further
2024-09-12 18:25:54 -04:00
bd1d1c5c5e
fix thumb "no fetches"
2024-09-08 11:10:31 -04:00
ceb5a9febe
draw (most of) the rest of the owl
2024-09-06 03:59:59 -04:00
299713e412
basic arm9 set up
2024-09-05 09:13:46 -04:00
2d081a6e02
improve arm7 timings
2024-09-01 18:03:32 -04:00
f0bd2b9051
Merge remote-tracking branch 'upstream/master' into interpreter-fixes
2024-08-30 19:33:16 -04:00
824eb370e4
Fix the build when the JIT is disabled ( #2139 )
2024-08-19 15:21:34 +02:00
332a39dbaf
fix JIT being borked
2024-08-05 16:14:17 -04:00
a85b2bfb56
tweak when irqs are triggered and fix prefetch aborts
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also ig add some comments next to the svc funcs so that someone searching for "swi" can find them easier
2024-08-05 14:57:17 -04:00
eedd2806f9
Reapply "Improve accuracy of prefetch aborts"
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This reverts commit 0dc619d615
2024-08-05 12:37:42 -04:00
0dc619d615
Revert "Improve accuracy of prefetch aborts"
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This reverts commit 587958e678
2024-08-05 11:41:25 -04:00
587958e678
Improve accuracy of prefetch aborts
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comes with a small-ish performance hit
2024-08-04 23:31:20 -04:00
fe69cfac7d
Merge remote-tracking branch 'upstream/master' into interpreter-fixes
2024-08-04 21:28:32 -04:00
dd386d12a9
use templates to only execute GDB stub related code if enabled
2024-08-05 03:23:49 +02:00
ab2a8f128f
revert timing tweaks, finish thumb interwork code
2024-08-04 14:54:36 -04:00
038ffa3a35
revert the *entire* interlock implemention
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too slow, not accurate enough.
we need to do a *lot* more research into the specifics of how this works with all the various aspects of the cpu's timings before we can make a good implementation
2024-07-11 20:08:35 -04:00
1fdac1d489
...why am i checking for dtcm?
2024-07-11 16:18:55 -04:00
e2be0b4f93
actually no it was not more correct
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undo previous commit because actually code cycles *do* matter
2024-07-07 15:42:10 -04:00
383750692e
doesn't really matter but idk it's more correct?
2024-07-06 12:38:39 -04:00
ea429a1b8d
improve interlock emulation
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add cycles to the instruction execution time rather than the timestamp directly.
2024-07-04 12:58:58 -04:00
bd1665c1d3
minor timing tweaks
2024-07-04 12:41:09 -04:00
0060958fed
Merge remote-tracking branch 'upstream/master' into jump-after-writeback
2024-07-03 15:26:58 -04:00
541e1e6388
proper timings for ldr/str
2024-06-25 09:08:11 -04:00
dbe00e72dd
improve stm timings
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need to verify if they apply to all store instructions
2024-06-24 22:50:04 -04:00
109bbed3d0
improve ldm timings
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I believe this also applies to other loads as well, but currently untested.
2024-06-24 20:22:38 -04:00
a973c0bf5b
initial implementation of interlock cycles
2024-06-15 16:07:36 -04:00
8fc403cdad
update copyright headers
2024-06-15 17:01:19 +02:00
5a174a2ce3
track interlock cycles for load instructions
2024-06-14 00:51:55 -04:00
3ddccde5b9
verified
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also remove no longer needed variable
2024-06-10 13:23:18 -04:00
ae0824fdd3
it all makes sense now...
2024-06-09 19:10:43 -04:00
b90d5c2320
what the actual F*** is going on
2024-06-09 12:18:31 -04:00
be60c68aeb
more weirdness
2024-06-09 07:25:42 -04:00
849d4e51ac
imma be real, i have no idea what is going on here
2024-06-08 22:12:44 -04:00
1871c48849
fix double data aborts with strd
2024-06-05 10:28:51 -04:00
Jaklyy