functional write buffer prototype
This commit is contained in:
Jaklyy
parent
c62f0f1244
commit
6e30cf3bfb
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@ -208,6 +208,9 @@ void ARMv5::Reset()
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Store = false;
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InterlockMask = 0;
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WBWritePointer = 16;
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WBFillPointer = 0;
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ARM::Reset();
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}
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@ -609,6 +612,7 @@ void ARMv5::Execute()
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else
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{
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NDS.ARM9Timestamp = NDS.ARM9Target;
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WriteBufferCheck();
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return;
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}
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}
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@ -742,6 +746,7 @@ void ARMv5::Execute()
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//NDS.ARM9Timestamp += Cycles;
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//Cycles = 0;
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}
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WriteBufferCheck();
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if (Halted == 2)
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Halted = 0;
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@ -757,7 +762,7 @@ void ARMv4::Execute()
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{
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if constexpr (mode == CPUExecuteMode::InterpreterGDB)
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GdbCheckB();
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if (Halted)
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{
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if (Halted == 2)
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13
src/ARM.h
13
src/ARM.h
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@ -291,11 +291,13 @@ public:
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void AddCycles_CDI() override
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{
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AddCycles_MW(DataCycles);
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DataCycles = 0;
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}
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void AddCycles_CD() override
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{
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AddCycles_MW(DataCycles);
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DataCycles = 0;
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}
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void GetCodeMemRegion(u32 addr, MemRegion* region);
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@ -314,6 +316,10 @@ public:
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void ICacheLookup(u32 addr);
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void ICacheInvalidateByAddr(u32 addr);
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void ICacheInvalidateAll();
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void WriteBufferCheck();
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void WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr = 0);
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void WriteBufferDrain();
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void CP15Write(u32 id, u32 val);
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u32 CP15Read(u32 id) const;
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@ -369,6 +375,13 @@ public:
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bool Store;
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u16 InterlockMask;
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u8 WBWritePointer;
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u8 WBFillPointer;
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u32 WBAddr; // current working address for the write buffer
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u32 storeaddr[16]; // debugging
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u64 WBCycles[16]; // timestamp each write will complete
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u64 WriteBufferFifo[16]; // 0-31: value | 62-63: 0 byte, 1 half, 2 word, 3 addr
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#ifdef GDBSTUB_ENABLED
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u32 ReadMem(u32 addr, int size) override;
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void WriteMem(u32 addr, int size, u32 v) override;
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506
src/CP15.cpp
506
src/CP15.cpp
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@ -172,13 +172,13 @@ void ARMv5::UpdatePURegion(u32 n)
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if (CP15Control & (1<<2))
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{
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datacache = (PU_DataCacheable >> n) & 0x1;
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datawrite = (PU_DataCacheWrite >> n) & 0x1;
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}
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else
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{
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datacache = 0;
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datawrite = 0;
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datacache = false;
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}
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datawrite = (PU_DataCacheWrite >> n) & 0x1;
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u32 rgn = PU_Region[n];
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if (!(rgn & (1<<0)))
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@ -224,12 +224,12 @@ void ARMv5::UpdatePURegion(u32 n)
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{
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privmask |= 0x10;
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usermask |= 0x10;
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if (datawrite & 0x1)
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{
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privmask |= 0x20;
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usermask |= 0x20;
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}
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}
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if (datawrite & 0x1)
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{
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privmask |= 0x20;
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usermask |= 0x20;
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}
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if (codecache & 0x1)
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@ -438,6 +438,223 @@ void ARMv5::ICacheInvalidateAll()
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ICacheTags[i] = 1;
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}
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void ARMv5::WriteBufferCheck()
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{
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if (WBWritePointer == 16) return;
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while (WBCycles[WBWritePointer] <= (NDS.ARM9Timestamp + DataCycles))
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{
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//printf("drainingwb %lli, %i %08X %i\n", WBCycles[WBWritePointer], WBWritePointer, WBAddr, WriteBufferFifo[WBWritePointer] >> 62);
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switch ((u64)WriteBufferFifo[WBWritePointer] >> 62)
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{
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case 0: // byte
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{
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u8 val = WriteBufferFifo[WBWritePointer] & 0xFF;
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if (WBAddr < ITCMSize)
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{
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*(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val;
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else BusWrite8(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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break;
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}
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case 1: // halfword
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{
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u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF;
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if (WBAddr < ITCMSize)
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{
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*(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val;
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else BusWrite16(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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break;
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}
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case 2: // word
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{
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u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
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if (WBAddr < ITCMSize)
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{
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*(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val;
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else BusWrite32(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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WBAddr += 4;
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break;
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}
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case 3: // address update
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WBAddr = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
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break;
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}
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WBWritePointer = (WBWritePointer + 1) & 0xF;
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if (WBWritePointer == WBFillPointer)
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{
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WBWritePointer = 16;
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WBFillPointer = 0;
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break;
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}
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}
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}
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void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr)
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{
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WriteBufferCheck();
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if (WBFillPointer == WBWritePointer)
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{
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//printf("forcedrainingwb %lli, %i %08X %i\n", WBCycles[WBWritePointer], WBWritePointer, WBAddr, WriteBufferFifo[WBWritePointer] >> 62);
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if (NDS.ARM9Timestamp < WBCycles[WBWritePointer])
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{
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NDS.ARM9Timestamp = WBCycles[WBWritePointer];
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DataCycles = 0; // checkme
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}
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switch ((u64)WriteBufferFifo[WBWritePointer] >> 62)
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{
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case 0: // byte
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{
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u8 val = WriteBufferFifo[WBWritePointer] & 0xFF;
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if (WBAddr < ITCMSize)
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{
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*(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val;
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else BusWrite8(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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break;
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}
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case 1: // halfword
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{
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u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF;
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if (WBAddr < ITCMSize)
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{
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*(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val;
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else BusWrite16(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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break;
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}
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case 2: // word
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{
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u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
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if (WBAddr < ITCMSize)
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{
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*(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val;
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else BusWrite32(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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WBAddr += 4;
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break;
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}
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case 3: // address update
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WBAddr = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
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break;
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}
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WBWritePointer = (WBWritePointer + 1) & 0xF;
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if (WBWritePointer == WBFillPointer)
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{
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WBWritePointer = 16;
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WBFillPointer = 0;
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}
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}
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//printf("fillingwb %lli %i %i %08X %i\n", NDS.ARM9Timestamp, WBWritePointer, WBFillPointer, val, flag);
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if (WBWritePointer == 16)
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{
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WBCycles[WBFillPointer] = NDS.ARM9Timestamp + DataCycles + cycles;
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WBWritePointer = 0;
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}
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else
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{
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WBCycles[WBFillPointer] = WBCycles[(WBFillPointer-1) & 0xF] + cycles;
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}
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WriteBufferFifo[WBFillPointer] = val | (u64)flag << 62;
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storeaddr[WBFillPointer] = addr;
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WBFillPointer = (WBFillPointer + 1) & 0xF;
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}
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void ARMv5::WriteBufferDrain()
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{
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if (WBWritePointer == 16) return;
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while (true)
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{
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//printf("fullydrainingwb %lli, %i %08X %i\n", WBCycles[WBWritePointer], WBWritePointer, WBAddr, WriteBufferFifo[WBWritePointer] >> 62);
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if (NDS.ARM9Timestamp < WBCycles[WBWritePointer])
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{
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NDS.ARM9Timestamp = WBCycles[WBWritePointer];
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DataCycles = 0; // checkme
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}
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switch (WriteBufferFifo[WBWritePointer] >> 62)
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{
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case 0: // byte
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{
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u8 val = WriteBufferFifo[WBWritePointer] & 0xFF;
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if (WBAddr < ITCMSize)
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{
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*(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val;
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else BusWrite8(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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break;
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}
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case 1: // halfword
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{
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u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF;
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if (WBAddr < ITCMSize)
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{
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*(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val;
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else BusWrite16(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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break;
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}
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case 2: // word
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{
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u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
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if (WBAddr < ITCMSize)
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{
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*(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
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}
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else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val;
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else BusWrite32(storeaddr[WBWritePointer], val);
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if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
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WBAddr += 4;
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break;
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}
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case 3: // address update
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WBAddr = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
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break;
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}
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WBWritePointer = (WBWritePointer + 1) & 0xF;
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if (WBWritePointer == WBFillPointer)
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{
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WBWritePointer = 16;
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WBFillPointer = 0;
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break;
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}
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}
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//printf("wbdrained\n");
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}
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void ARMv5::CP15Write(u32 id, u32 val)
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{
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@ -788,6 +1005,9 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
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return 0;
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}
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if ((PU_Map[addr>>12] & 0x30))
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WriteBufferDrain();
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if (addr < ITCMSize)
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{
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CodeCycles = 1;
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@ -837,6 +1057,9 @@ bool ARMv5::DataRead8(u32 addr, u32* val)
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DataCycles = 1;
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return false;
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}
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if ((PU_Map[addr>>12] & 0x30))
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WriteBufferDrain();
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if (addr < ITCMSize)
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{
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@ -882,6 +1105,8 @@ bool ARMv5::DataRead16(u32 addr, u32* val)
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}
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addr &= ~1;
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if ((PU_Map[addr>>CP15_MAP_ENTRYSIZE_LOG2] & (CP15_MAP_DCACHEWRITEBACK | CP15_MAP_DCACHEABLE)))
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WriteBufferDrain();
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if (addr < ITCMSize)
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{
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@ -928,6 +1153,9 @@ bool ARMv5::DataRead32(u32 addr, u32* val)
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addr &= ~3;
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if ((PU_Map[addr>>12] & 0x30))
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WriteBufferDrain();
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if (addr < ITCMSize)
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{
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DataCycles = 1;
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@ -972,6 +1200,9 @@ bool ARMv5::DataRead32S(u32 addr, u32* val)
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addr &= ~3;
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if ((PU_Map[addr>>12] & 0x30))
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WriteBufferDrain();
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if (addr < ITCMSize)
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{
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DataCycles += 1;
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@ -1016,37 +1247,46 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
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return false;
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}
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if (addr < ITCMSize)
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if (!(PU_Map[addr>>12] & (0x30)))
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{
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DataCycles = 1;
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ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
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DataRegion = Mem9_ITCM;
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*(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
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return true;
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}
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if ((addr & DTCMMask) == DTCMBase)
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{
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DataCycles = 1;
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DataRegion = Mem9_DTCM;
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*(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
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return true;
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}
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NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
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if (addr < ITCMSize)
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{
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DataCycles = 1;
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ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
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DataRegion = Mem9_ITCM;
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*(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
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return true;
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}
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if ((addr & DTCMMask) == DTCMBase)
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{
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DataCycles = 1;
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DataRegion = Mem9_DTCM;
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*(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
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return true;
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}
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DataCycles = MemTimings[addr >> 12][1];
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NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
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DataCycles = MemTimings[addr >> 12][1];
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if ((addr >> 24) == 0x02)
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp;
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DataRegion = Mem9_MainRAM;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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DataCycles -= (2<<NDS.ARM9ClockShift);
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if ((addr >> 24) == 0x02)
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp;
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DataRegion = Mem9_MainRAM;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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DataCycles -= (2<<NDS.ARM9ClockShift);
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}
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else DataRegion = NDS.ARM9Regions[addr>>14];
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BusWrite8(addr, val);
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}
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else
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{
|
||||
DataCycles = 1;
|
||||
WriteBufferWrite(addr, 3, 1);
|
||||
WriteBufferWrite(val, 0, MemTimings[addr >> 12][1], addr);
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite8(addr, val);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1063,37 +1303,47 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
|
|||
|
||||
addr &= ~1;
|
||||
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataCycles = 1;
|
||||
ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_ITCM;
|
||||
*(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
|
||||
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
|
||||
return true;
|
||||
}
|
||||
if ((addr & DTCMMask) == DTCMBase)
|
||||
{
|
||||
DataCycles = 1;
|
||||
DataRegion = Mem9_DTCM;
|
||||
*(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||
if (!(PU_Map[addr>>12] & 0x30))
|
||||
{
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataCycles = 1;
|
||||
ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_ITCM;
|
||||
*(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
|
||||
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
|
||||
return true;
|
||||
}
|
||||
if ((addr & DTCMMask) == DTCMBase)
|
||||
{
|
||||
DataCycles = 1;
|
||||
DataRegion = Mem9_DTCM;
|
||||
*(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
DataCycles = MemTimings[addr >> 12][1];
|
||||
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||
|
||||
DataCycles = MemTimings[addr >> 12][1];
|
||||
|
||||
if ((addr >> 24) == 0x02)
|
||||
{
|
||||
if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp;
|
||||
DataRegion = Mem9_MainRAM;
|
||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataCycles -= (2<<NDS.ARM9ClockShift);
|
||||
if ((addr >> 24) == 0x02)
|
||||
{
|
||||
if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp;
|
||||
DataRegion = Mem9_MainRAM;
|
||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataCycles -= (2<<NDS.ARM9ClockShift);
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite16(addr, val);
|
||||
}
|
||||
else
|
||||
{
|
||||
DataCycles = 1;
|
||||
WriteBufferWrite(addr, 3, 1);
|
||||
WriteBufferWrite(val, 1, MemTimings[addr >> 12][1], addr);
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite16(addr, val);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1110,37 +1360,47 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
|
|||
|
||||
addr &= ~3;
|
||||
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataCycles = 1;
|
||||
ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_ITCM;
|
||||
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
|
||||
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
|
||||
return true;
|
||||
}
|
||||
if ((addr & DTCMMask) == DTCMBase)
|
||||
{
|
||||
DataCycles = 1;
|
||||
DataRegion = Mem9_DTCM;
|
||||
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||
if (!(PU_Map[addr>>12] & 0x30))
|
||||
{
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataCycles = 1;
|
||||
ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_ITCM;
|
||||
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
|
||||
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
|
||||
return true;
|
||||
}
|
||||
if ((addr & DTCMMask) == DTCMBase)
|
||||
{
|
||||
DataCycles = 1;
|
||||
DataRegion = Mem9_DTCM;
|
||||
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
DataCycles = MemTimings[addr >> 12][2];
|
||||
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||
|
||||
DataCycles = MemTimings[addr >> 12][2];
|
||||
|
||||
if ((addr >> 24) == 0x02)
|
||||
{
|
||||
if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp;
|
||||
DataRegion = Mem9_MainRAM;
|
||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataCycles -= (2<<NDS.ARM9ClockShift);
|
||||
if ((addr >> 24) == 0x02)
|
||||
{
|
||||
if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp;
|
||||
DataRegion = Mem9_MainRAM;
|
||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataCycles -= (2<<NDS.ARM9ClockShift);
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite32(addr, val);
|
||||
}
|
||||
else
|
||||
{
|
||||
DataCycles = 1;
|
||||
WriteBufferWrite(addr, 3, 1);
|
||||
WriteBufferWrite(val, 2, MemTimings[addr >> 12][2], addr);
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite32(addr, val);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1156,38 +1416,46 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val)
|
|||
|
||||
addr &= ~3;
|
||||
|
||||
if (addr < ITCMSize)
|
||||
|
||||
if (!(PU_Map[addr>>12] & 0x30))
|
||||
{
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataCycles += 1;
|
||||
ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_ITCM;
|
||||
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
|
||||
#ifdef JIT_ENABLED
|
||||
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
|
||||
#endif
|
||||
return true;
|
||||
}
|
||||
if ((addr & DTCMMask) == DTCMBase)
|
||||
{
|
||||
DataCycles += 1;
|
||||
DataRegion = Mem9_DTCM;
|
||||
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||
|
||||
if ((addr >> 24) == 0x02)
|
||||
{
|
||||
if ((DataRegion != Mem9_MainRAM) && ((NDS.ARM9Timestamp + DataCycles) < MainRAMTimestamp)) NDS.ARM9Timestamp = MainRAMTimestamp - DataCycles;
|
||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_MainRAM;
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite32(addr, val);
|
||||
DataCycles += MemTimings[addr >> 12][3];
|
||||
}
|
||||
else
|
||||
{
|
||||
DataCycles += 1;
|
||||
ITCMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_ITCM;
|
||||
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
|
||||
#ifdef JIT_ENABLED
|
||||
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
|
||||
#endif
|
||||
return true;
|
||||
WriteBufferWrite(val, 2, MemTimings[addr >> 12][3], addr);
|
||||
}
|
||||
if ((addr & DTCMMask) == DTCMBase)
|
||||
{
|
||||
DataCycles += 1;
|
||||
DataRegion = Mem9_DTCM;
|
||||
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||
|
||||
|
||||
if ((addr >> 24) == 0x02)
|
||||
{
|
||||
if ((DataRegion != Mem9_MainRAM) && ((NDS.ARM9Timestamp + DataCycles) < MainRAMTimestamp)) NDS.ARM9Timestamp = MainRAMTimestamp - DataCycles;
|
||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
||||
DataRegion = Mem9_MainRAM;
|
||||
}
|
||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
||||
|
||||
BusWrite32(addr, val);
|
||||
DataCycles += MemTimings[addr >> 12][3];
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue