writing back dirty cache lines should be done in one burst if both halves are dirty
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e783e778eb
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12
src/CP15.cpp
12
src/CP15.cpp
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@ -1091,12 +1091,20 @@ void ARMv5::DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine)
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u8 cycless = NDS.ARM9MemTimings[tag>>14][3];
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u8 cycless = NDS.ARM9MemTimings[tag>>14][3];
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if ((tag >> 24) == 0x02) cycless = (cycless - 2) | 0x80;
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if ((tag >> 24) == 0x02) cycless = (cycless - 2) | 0x80;
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if (DCacheTags[index] & CACHE_FLAG_DIRTY_LOWERHALF)
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{
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cyclesn = cycless; // write back is done in one burst if both halves are dirty
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}
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else
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{
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WriteBufferWrite(tag+0x10, 3, 0);
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WriteBufferWrite(tag+0x10, 3, 0);
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NDS.ARM9Timestamp += 1;
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}
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WriteBufferWrite(ptr[4], 2, cyclesn, tag+0x10);
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WriteBufferWrite(ptr[4], 2, cyclesn, tag+0x10);
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WriteBufferWrite(ptr[5], 2, cycless, tag+0x14);
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WriteBufferWrite(ptr[5], 2, cycless, tag+0x14);
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WriteBufferWrite(ptr[6], 2, cycless, tag+0x18);
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WriteBufferWrite(ptr[6], 2, cycless, tag+0x18);
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WriteBufferWrite(ptr[7], 2, cycless, tag+0x1C);
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WriteBufferWrite(ptr[7], 2, cycless, tag+0x1C);
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NDS.ARM9Timestamp += 5; //DataCycles += 5; CHECKME: does this function like a write does but with mcr?
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NDS.ARM9Timestamp += 4;
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}
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}
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DCacheTags[index] &= ~(CACHE_FLAG_DIRTY_LOWERHALF | CACHE_FLAG_DIRTY_UPPERHALF);
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DCacheTags[index] &= ~(CACHE_FLAG_DIRTY_LOWERHALF | CACHE_FLAG_DIRTY_UPPERHALF);
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#endif
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#endif
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@ -2274,7 +2282,7 @@ bool ARMv5::DataRead32S(u32 addr, u32* val)
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if (NDS.ARM9Timestamp < time) NDS.ARM9Timestamp = time;
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if (NDS.ARM9Timestamp < time) NDS.ARM9Timestamp = time;
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}
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}
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if (PU_Map[addr>>12] & 0x30)
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if (PU_Map[addr>>12] & 0x30) // checkme
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WriteBufferDrain();
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WriteBufferDrain();
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NDS.ARM9Timestamp += DataCycles;
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NDS.ARM9Timestamp += DataCycles;
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