handle uncached/buffered accesses for arm9
This commit is contained in:
parent
70dca68de2
commit
db7eb564f0
132
src/CP15.cpp
132
src/CP15.cpp
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@ -2102,13 +2102,9 @@ void ARMv5::CodeRead32(u32 addr)
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
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FetchAddr[16] = addr;
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NDS.ARM9Timestamp += cycles;
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MRTrack.Type = MainRAMType::Fetch;
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if (NDS.ARM9ClockShift == 2)
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MRTrack.Var = MRCodeFetch | MR32;
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{
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MainRAMTimestamp = NDS.ARM9Timestamp;
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NDS.ARM9Timestamp -= 4;
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}
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}
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}
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else
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else
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{
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{
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@ -2117,16 +2113,15 @@ void ARMv5::CodeRead32(u32 addr)
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += cycles;
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NDS.ARM9Timestamp += cycles;
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}
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Store = false;
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if (WBTimestamp < ((NDS.ARM9Timestamp - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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if (NDS.ARM9Timestamp < TimestampActual) NDS.ARM9Timestamp = TimestampActual;
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DataRegion = Mem9_Null;
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RetVal = BusRead32(addr);
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RetVal = BusRead32(addr);
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}
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Store = false;
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DataRegion = Mem9_Null;
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return;
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return;
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}
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}
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@ -2236,21 +2231,20 @@ void ARMv5::DRead8_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Var = MR8;
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if (NDS.ARM9ClockShift == 2) DataCycles -= 4;
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MRTrack.Progress = reg;
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DataRegion = Mem9_MainRAM;
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}
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}
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else
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else
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{
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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DataRegion = NDS.ARM9Regions[addr>>14];
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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}
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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*val = BusRead8(addr);
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*val = BusRead8(addr);
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}
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}
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}
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bool ARMv5::DataRead16(u32 addr, u8 reg)
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bool ARMv5::DataRead16(u32 addr, u8 reg)
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@ -2334,21 +2328,20 @@ void ARMv5::DRead16_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Var = MR16;
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if (NDS.ARM9ClockShift == 2) DataCycles -= 4;
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MRTrack.Progress = reg;
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DataRegion = Mem9_MainRAM;
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}
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}
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else
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else
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{
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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DataRegion = NDS.ARM9Regions[addr>>14];
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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}
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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*val = BusRead16(addr);
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*val = BusRead16(addr);
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}
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}
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}
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bool ARMv5::DataRead32(u32 addr, u8 reg)
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bool ARMv5::DataRead32(u32 addr, u8 reg)
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@ -2435,21 +2428,20 @@ void ARMv5::DRead32_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Var = MR32;
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if (NDS.ARM9ClockShift == 2) DataCycles -= 4;
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MRTrack.Progress = reg;
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DataRegion = Mem9_MainRAM;
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}
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}
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else
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else
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{
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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DataRegion = NDS.ARM9Regions[addr>>14];
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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}
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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*val = BusRead32(addr);
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*val = BusRead32(addr);
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}
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LDRRegs &= ~1<<reg;
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LDRRegs &= ~1<<reg;
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}
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}
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@ -2533,15 +2525,19 @@ void ARMv5::DRead32S_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Type = MainRAMType::Fetch;
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if (NDS.ARM9ClockShift == 2) MainRAMTimestamp += 4;
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MRTrack.Var = MR32 | MRSequential;
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DataRegion = Mem9_MainRAM;
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MRTrack.Progress = reg;
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}
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}
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else
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else
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{
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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DataRegion = NDS.ARM9Regions[addr>>14];
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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*val = BusRead32(addr);
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}
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}
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}
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}
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else // ns
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else // ns
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@ -2552,22 +2548,21 @@ void ARMv5::DRead32S_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Var = MR32;
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if (NDS.ARM9ClockShift == 2) DataCycles -= 4;
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MRTrack.Progress = reg;
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DataRegion = Mem9_MainRAM;
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}
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}
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else
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else
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{
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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DataRegion = NDS.ARM9Regions[addr>>14];
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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if ((NDS.ARM9Timestamp <= WBReleaseTS) && (DataRegion == WBLastRegion)) // check write buffer
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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NDS.ARM9Timestamp += 1<<NDS.ARM9ClockShift;
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}
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}
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles - (3<<NDS.ARM9ClockShift) + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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*val = BusRead32(addr);
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*val = BusRead32(addr);
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}
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}
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LDRRegs &= ~1<<reg;
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LDRRegs &= ~1<<reg;
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}
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}
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@ -2652,17 +2647,19 @@ void ARMv5::DWrite8_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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DataRegion = Mem9_MainRAM;
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MRTrack.Var = MRWrite | MR8;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Progress = reg;
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DataCycles -= 1<<NDS.ARM9ClockShift;
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}
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}
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else DataRegion = NDS.ARM9Regions[addr>>14];
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else
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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BusWrite8(addr, val);
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BusWrite8(addr, val);
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}
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}
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}
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else
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else
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{
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{
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if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
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if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
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@ -2758,17 +2755,19 @@ void ARMv5::DWrite16_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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DataRegion = Mem9_MainRAM;
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MRTrack.Var = MRWrite | MR16;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Progress = reg;
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DataCycles -= 2<<NDS.ARM9ClockShift;
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}
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}
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else DataRegion = NDS.ARM9Regions[addr>>14];
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else
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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BusWrite16(addr, val);
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BusWrite16(addr, val);
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}
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}
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}
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else
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else
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{
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{
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if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
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if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
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@ -2869,17 +2868,19 @@ void ARMv5::DWrite32_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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MRTrack.Type = MainRAMType::Fetch;
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DataRegion = Mem9_MainRAM;
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MRTrack.Var = MRWrite | MR32;
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Progress = reg;
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DataCycles -= 2<<NDS.ARM9ClockShift;
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}
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}
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else DataRegion = NDS.ARM9Regions[addr>>14];
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else
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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BusWrite32(addr, val);
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BusWrite32(addr, val);
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}
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}
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}
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else
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else
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{
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{
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if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
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if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
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@ -2977,11 +2978,18 @@ void ARMv5::DWrite32S_2()
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if ((addr >> 24) == 0x02)
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if ((addr >> 24) == 0x02)
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{
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{
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MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
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MRTrack.Type = MainRAMType::Fetch;
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MainRAMTimestamp += 2<<NDS.ARM9ClockShift;
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MRTrack.Var = MRWrite | MR32 | MRSequential;
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DataRegion = Mem9_MainRAM;
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MRTrack.Progress = reg;
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}
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else
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{
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DataRegion = NDS.ARM9Regions[addr>>14];
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if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
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WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
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BusWrite32(addr, val);
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}
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}
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else DataRegion = NDS.ARM9Regions[addr>>14];
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// burst stores seem to process the extra delay cycles at the end of the burst
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// burst stores seem to process the extra delay cycles at the end of the burst
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// this means that we end up *always* able to begin code fetches 3 cycles early when accessing the bus
|
// this means that we end up *always* able to begin code fetches 3 cycles early when accessing the bus
|
||||||
|
@ -2997,18 +3005,20 @@ void ARMv5::DWrite32S_2()
|
||||||
|
|
||||||
if ((addr >> 24) == 0x02)
|
if ((addr >> 24) == 0x02)
|
||||||
{
|
{
|
||||||
if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = (MainRAMTimestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
|
MRTrack.Type = MainRAMType::Fetch;
|
||||||
MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles;
|
MRTrack.Var = MRWrite | MR32;
|
||||||
DataCycles -= 2<<NDS.ARM9ClockShift;
|
MRTrack.Progress = reg;
|
||||||
DataRegion = Mem9_MainRAM;
|
|
||||||
}
|
|
||||||
else DataRegion = NDS.ARM9Regions[addr>>14];
|
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DataRegion = NDS.ARM9Regions[addr>>14];
|
||||||
|
|
||||||
if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
|
if (WBTimestamp < ((NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1)))
|
||||||
WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
|
WBTimestamp = (NDS.ARM9Timestamp + DataCycles + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
|
||||||
BusWrite32(addr, val);
|
BusWrite32(addr, val);
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
WriteBufferWrite(val, 3, addr);
|
WriteBufferWrite(val, 3, addr);
|
||||||
|
|
61
src/NDS.cpp
61
src/NDS.cpp
|
@ -922,6 +922,67 @@ void NDS::MainRAMHandleARM9()
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
case MainRAMType::Fetch:
|
||||||
|
{
|
||||||
|
u8 var = ARM9.MRTrack.Var;
|
||||||
|
|
||||||
|
if ((var & MRSequential) && A9WENTLAST)
|
||||||
|
{
|
||||||
|
MainRAMTimestamp = A9ContentionTS += 2;
|
||||||
|
ARM9.DataCycles = 2 << ARM9ClockShift;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; }
|
||||||
|
|
||||||
|
MainRAMTimestamp = A9ContentionTS + (var & MR16) ? 8 : 9; // checkme: are these correct for 8bit?
|
||||||
|
if (var & MRWrite) A9ContentionTS += (var & MR16) ? 5 : 6; // checkme: is this correct for 133mhz?
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (ARM9ClockShift == 1) A9ContentionTS += (var & MR16) ? 8 : 9;
|
||||||
|
else A9ContentionTS += (var & MR16) ? 7 : 8;
|
||||||
|
ARM9.DataCycles = 3 << ARM9ClockShift;
|
||||||
|
}
|
||||||
|
MainRAMLastAccess = A9LAST;
|
||||||
|
}
|
||||||
|
ARM9Timestamp = A9ContentionTS << ARM9ClockShift;
|
||||||
|
|
||||||
|
if (var & MRCodeFetch)
|
||||||
|
{
|
||||||
|
u32 addr = ARM9.FetchAddr[16];
|
||||||
|
ARM9.RetVal = ARM9Read32(addr);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u8 reg = ARM9.MRTrack.Progress;
|
||||||
|
u32 addr = ARM9.FetchAddr[reg];
|
||||||
|
if (var & MRWrite) // write
|
||||||
|
{
|
||||||
|
u32 val = ARM9.STRVal[reg];
|
||||||
|
if (var & MR32) ARM9Write32(addr, val);
|
||||||
|
else if (var & MR16) ARM9Write16(addr, val);
|
||||||
|
else ARM9Write8 (addr, val);
|
||||||
|
}
|
||||||
|
else // read
|
||||||
|
{
|
||||||
|
u32 dummy;
|
||||||
|
u32* val = (ARM9.LDRFailedRegs & (1<<reg)) ? &dummy : &ARM9.R[reg];
|
||||||
|
if (var & MR32) *val = ARM9Read32(addr);
|
||||||
|
else if (var & MR16) *val = ARM9Read16(addr);
|
||||||
|
else *val = ARM9Read8 (addr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int sub = 0;
|
||||||
|
if (var & MRWrite) sub = 3<<ARM9ClockShift;
|
||||||
|
|
||||||
|
u64 ts = (ARM9Timestamp - sub + ((1<<ARM9ClockShift)-1)) & ~((1<<ARM9ClockShift)-1);
|
||||||
|
if (ARM9.WBTimestamp < ts) ARM9.WBTimestamp = ts;
|
||||||
|
|
||||||
|
memset(&ARM9.MRTrack, 0, sizeof(ARM9.MRTrack));
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
case MainRAMType::ICacheStream:
|
case MainRAMType::ICacheStream:
|
||||||
{
|
{
|
||||||
u8* prog = &ARM9.MRTrack.Progress;
|
u8* prog = &ARM9.MRTrack.Progress;
|
||||||
|
|
Loading…
Reference in New Issue