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code reads should trigger an edge case with dcache streaming 

also itcm and icache behave similarly with itcm fetches
and apparently i forgot to commit the fix to stm too oops--
This commit is contained in:
Jaklyy 2024-10-29 19:56:18 -04:00
parent ce55f29d9d
commit c50d15d03e
3 changed files with 20 additions and 6 deletions
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1
src/ARM.h
View File

@ -281,6 +281,7 @@ public:
void AddCycles_CD() override void AddCycles_CD() override
{ {
Store = true;
AddCycles_MW(DataCycles); AddCycles_MW(DataCycles);
DataCycles = 0; DataCycles = 0;
} }

3
src/ARMInterpreter_LoadStore.cpp
View File

@ -160,10 +160,7 @@ void StoreSingle(ARM* cpu, u8 rd, u8 rn, s32 offset, u16 ilmask)
} }
if (cpu->Num == 0) if (cpu->Num == 0)
{
((ARMv5*)cpu)->HandleInterlocksMemory(rd); ((ARMv5*)cpu)->HandleInterlocksMemory(rd);
((ARMv5*)cpu)->Store = true;
}
bool dabort; bool dabort;
if constexpr (size == 8) dabort = !cpu->DataWrite8 (addr, storeval); if constexpr (size == 8) dabort = !cpu->DataWrite8 (addr, storeval);

22
src/CP15.cpp
View File

@ -411,7 +411,11 @@ u32 ARMv5::ICacheLookup(const u32 addr)
{ {
u32 *cacheLine = (u32 *)&ICache[(id+set) << ICACHE_LINELENGTH_LOG2]; u32 *cacheLine = (u32 *)&ICache[(id+set) << ICACHE_LINELENGTH_LOG2];
if (ICacheFillPtr == 7) NDS.ARM9Timestamp++; if (ICacheFillPtr == 7)
{
if (NDS.ARM9Timestamp < ITCMTimestamp) NDS.ARM9Timestamp = ITCMTimestamp; // does this apply to streamed fetches?
NDS.ARM9Timestamp++;
}
else else
{ {
u64 nextfill = ICacheFillTimes[ICacheFillPtr++]; u64 nextfill = ICacheFillTimes[ICacheFillPtr++];
@ -423,7 +427,11 @@ u32 ARMv5::ICacheLookup(const u32 addr)
{ {
u64 fillend = ICacheFillTimes[6] + 2; u64 fillend = ICacheFillTimes[6] + 2;
if (NDS.ARM9Timestamp < fillend) NDS.ARM9Timestamp = fillend; if (NDS.ARM9Timestamp < fillend) NDS.ARM9Timestamp = fillend;
else NDS.ARM9Timestamp++; else // checkme
{
if (NDS.ARM9Timestamp < ITCMTimestamp) NDS.ARM9Timestamp = ITCMTimestamp;
NDS.ARM9Timestamp++;
}
ICacheFillPtr = 7; ICacheFillPtr = 7;
} }
} }
@ -2014,6 +2022,13 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
} }
#endif #endif
} }
// bus reads can only overlap with dcache streaming by 6 cycles
if (DCacheFillPtr != 7)
{
u64 time = DCacheFillTimes[6] - 6; // checkme: minus 6?
if (NDS.ARM9Timestamp < time) NDS.ARM9Timestamp = time;
}
u8 cycles = MemTimings[addr >> 14][1]; u8 cycles = MemTimings[addr >> 14][1];
@ -2093,7 +2108,7 @@ bool ARMv5::DataRead8(u32 addr, u32* val)
#endif #endif
// bus reads can only overlap with icache streaming by 6 cycles // bus reads can only overlap with icache streaming by 6 cycles
// checkme: does cache trigger this? // checkme: does dcache trigger this?
if (ICacheFillPtr != 7) if (ICacheFillPtr != 7)
{ {
u64 time = ICacheFillTimes[6] - 6; // checkme: minus 6? u64 time = ICacheFillTimes[6] - 6; // checkme: minus 6?
@ -2695,6 +2710,7 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val)
if (!(PU_Map[addr>>12] & 0x30)) // non-bufferable if (!(PU_Map[addr>>12] & 0x30)) // non-bufferable
{ {
NDS.ARM9Timestamp = (NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
// bursts cannot cross a 1kb boundary // bursts cannot cross a 1kb boundary
if (addr & 0x3FF) // s if (addr & 0x3FF) // s
{ {