From c50d15d03e4327e1bb2f0229193714e25431a745 Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Tue, 29 Oct 2024 19:56:18 -0400
Subject: [PATCH] code reads should trigger an edge case with dcache streaming

also itcm and icache behave similarly with itcm fetches
and apparently i forgot to commit the fix to stm too oops--
---
 src/ARM.h                        |  1 +
 src/ARMInterpreter_LoadStore.cpp |  3 ---
 src/CP15.cpp                     | 22 +++++++++++++++++++---
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/ARM.h b/src/ARM.h
index 657e2069..8795d4c5 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -281,6 +281,7 @@ public:
 
     void AddCycles_CD() override
     {
+        Store = true;
         AddCycles_MW(DataCycles);
         DataCycles = 0;
     }
diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 3e3841de..c5b25eb2 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -160,10 +160,7 @@ void StoreSingle(ARM* cpu, u8 rd, u8 rn, s32 offset, u16 ilmask)
     }
 
     if (cpu->Num == 0)
-    {
         ((ARMv5*)cpu)->HandleInterlocksMemory(rd);
-        ((ARMv5*)cpu)->Store = true;
-    }
 
     bool dabort;
     if constexpr (size == 8)  dabort = !cpu->DataWrite8 (addr, storeval);
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 2d31ed71..0145e9df 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -411,7 +411,11 @@ u32 ARMv5::ICacheLookup(const u32 addr)
         {
             u32 *cacheLine = (u32 *)&ICache[(id+set) << ICACHE_LINELENGTH_LOG2];
 
-            if (ICacheFillPtr == 7) NDS.ARM9Timestamp++;
+            if (ICacheFillPtr == 7)
+            {
+                if (NDS.ARM9Timestamp < ITCMTimestamp) NDS.ARM9Timestamp = ITCMTimestamp; // does this apply to streamed fetches?
+                NDS.ARM9Timestamp++;
+            }
             else
             {
                 u64 nextfill = ICacheFillTimes[ICacheFillPtr++];
@@ -423,7 +427,11 @@ u32 ARMv5::ICacheLookup(const u32 addr)
                 {
                     u64 fillend = ICacheFillTimes[6] + 2;
                     if (NDS.ARM9Timestamp < fillend) NDS.ARM9Timestamp = fillend;
-                    else NDS.ARM9Timestamp++;
+                    else // checkme
+                    {
+                        if (NDS.ARM9Timestamp < ITCMTimestamp) NDS.ARM9Timestamp = ITCMTimestamp;
+                        NDS.ARM9Timestamp++;
+                    }
                     ICacheFillPtr = 7;
                 }
             }
@@ -2014,6 +2022,13 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
             }
     #endif 
         }
+    
+    // bus reads can only overlap with dcache streaming by 6 cycles
+    if (DCacheFillPtr != 7)
+    {
+        u64 time = DCacheFillTimes[6] - 6; // checkme: minus 6?
+        if (NDS.ARM9Timestamp < time) NDS.ARM9Timestamp = time;
+    }
 
     u8 cycles = MemTimings[addr >> 14][1];
     
@@ -2093,7 +2108,7 @@ bool ARMv5::DataRead8(u32 addr, u32* val)
     #endif
     
     // bus reads can only overlap with icache streaming by 6 cycles
-    // checkme: does cache trigger this?
+    // checkme: does dcache trigger this?
     if (ICacheFillPtr != 7)
     {
         u64 time = ICacheFillTimes[6] - 6; // checkme: minus 6?
@@ -2695,6 +2710,7 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val)
 
     if (!(PU_Map[addr>>12] & 0x30)) // non-bufferable
     {
+        NDS.ARM9Timestamp = (NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1)) & ~((1<<NDS.ARM9ClockShift)-1);
         // bursts cannot cross a 1kb boundary
         if (addr & 0x3FF) // s
         {