Added CP15 Trace Process ID
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81c9434116
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@ -332,8 +332,6 @@ public:
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void DCacheClearByAddr(const u32 addr);
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void DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine);
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void CP15Write(u32 id, u32 val);
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u32 CP15Read(u32 id) const;
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@ -344,6 +342,7 @@ public:
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u32 DTCMSetting, ITCMSetting;
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u32 DCacheLockDown, ICacheLockDown;
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u32 CacheDebugRegisterIndex;
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u32 CP15TraceProcessId;
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// for aarch64 JIT they need to go up here
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// to be addressable by a 12-bit immediate
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22
src/CP15.cpp
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src/CP15.cpp
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@ -40,6 +40,16 @@ const int kDataCacheTiming = 3;//2;
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const int kCodeCacheTiming = 3;//5;
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/* CP15 Reset sets the default values within each registers and
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memories of the CP15.
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This includes the Settings for
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DTCM
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ITCM
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Caches
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Regions
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Process Trace
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*/
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void ARMv5::CP15Reset()
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{
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CP15Control = 0x2078; // dunno
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@ -68,6 +78,8 @@ void ARMv5::CP15Reset()
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DCacheInvalidateAll();
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DCacheCount = 0;
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CP15TraceProcessId = 0;
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PU_CodeCacheable = 0;
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PU_DataCacheable = 0;
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PU_DataCacheWrite = 0;
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@ -103,6 +115,7 @@ void ARMv5::CP15DoSavestate(Savestate* file)
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file->Var32(&DCacheLockDown);
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file->Var32(&ICacheLockDown);
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file->Var32(&CacheDebugRegisterIndex);
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file->Var32(&CP15TraceProcessId);
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file->Var32(&PU_CodeCacheable);
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file->Var32(&PU_DataCacheable);
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@ -1086,6 +1099,11 @@ void ARMv5::CP15Write(u32 id, u32 val)
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UpdateITCMSetting();
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return;
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case 0xD01:
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case 0xD11:
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CP15TraceProcessId = val;
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return;
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case 0xF00:
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if (PU_Map != PU_PrivMap)
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{
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@ -1277,6 +1295,10 @@ u32 ARMv5::CP15Read(u32 id) const
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case 0x911:
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return ITCMSetting;
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case 0xD01: // See arm946E-S Rev 1 technical Reference Manual, Chapter 2.3.13 */
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case 0xD11: // backwards compatible read/write of the same register
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return CP15TraceProcessId;
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case 0xF00:
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if (PU_Map != PU_PrivMap)
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{
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