diff --git a/src/ARM.h b/src/ARM.h
index df06e84e..e56534ad 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -332,8 +332,6 @@ public:
     void DCacheClearByAddr(const u32 addr);
     void DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine);
 
-
-
     void CP15Write(u32 id, u32 val);
     u32 CP15Read(u32 id) const;
 
@@ -344,6 +342,7 @@ public:
     u32 DTCMSetting, ITCMSetting;
     u32 DCacheLockDown, ICacheLockDown;
     u32 CacheDebugRegisterIndex;
+    u32 CP15TraceProcessId;
 
     // for aarch64 JIT they need to go up here
     // to be addressable by a 12-bit immediate
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 714e591d..caa8de34 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -40,6 +40,16 @@ const int kDataCacheTiming = 3;//2;
 const int kCodeCacheTiming = 3;//5;
 
 
+/* CP15 Reset sets the default values within each registers and 
+   memories of the CP15. 
+   This includes the Settings for 
+        DTCM
+        ITCM
+        Caches
+        Regions
+        Process Trace
+*/
+
 void ARMv5::CP15Reset()
 {
     CP15Control = 0x2078; // dunno
@@ -68,6 +78,8 @@ void ARMv5::CP15Reset()
     DCacheInvalidateAll();
     DCacheCount = 0;
 
+    CP15TraceProcessId = 0;
+
     PU_CodeCacheable = 0;
     PU_DataCacheable = 0;
     PU_DataCacheWrite = 0;
@@ -103,6 +115,7 @@ void ARMv5::CP15DoSavestate(Savestate* file)
     file->Var32(&DCacheLockDown);
     file->Var32(&ICacheLockDown);
     file->Var32(&CacheDebugRegisterIndex);
+    file->Var32(&CP15TraceProcessId);
 
     file->Var32(&PU_CodeCacheable);
     file->Var32(&PU_DataCacheable);
@@ -1086,6 +1099,11 @@ void ARMv5::CP15Write(u32 id, u32 val)
         UpdateITCMSetting();
         return;
 
+    case 0xD01:
+    case 0xD11:
+        CP15TraceProcessId = val;
+        return;
+
     case 0xF00:
         if (PU_Map != PU_PrivMap)
         {            
@@ -1277,6 +1295,10 @@ u32 ARMv5::CP15Read(u32 id) const
     case 0x911:
         return ITCMSetting;
 
+    case 0xD01: // See arm946E-S Rev 1 technical Reference Manual, Chapter 2.3.13 */ 
+    case 0xD11: // backwards compatible read/write of the same register
+        return CP15TraceProcessId;
+
     case 0xF00:
         if (PU_Map != PU_PrivMap)
         {