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improve accuracy of prefetch abort handling slightly 

prefetch aborts should be handled on executing an instruction by a flag set when the instruction is fetched
This commit is contained in:
Jaklyy 2024-11-07 20:16:19 -05:00
parent ef5de6091b
commit 5091061a39
4 changed files with 10 additions and 10 deletions
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8
src/ARM.cpp
View File

@ -222,7 +222,7 @@ void ARM::DoSavestate(Savestate* file)
file->VarArray(R_ABT, 3*sizeof(u32)); file->VarArray(R_ABT, 3*sizeof(u32));
file->VarArray(R_IRQ, 3*sizeof(u32)); file->VarArray(R_IRQ, 3*sizeof(u32));
file->VarArray(R_UND, 3*sizeof(u32)); file->VarArray(R_UND, 3*sizeof(u32));
file->Var32(&CurInstr); file->Var64(&CurInstr);
#ifdef JIT_ENABLED #ifdef JIT_ENABLED
if (file->Saving && NDS.IsJITEnabled()) if (file->Saving && NDS.IsJITEnabled())
{ {
@ -232,7 +232,7 @@ void ARM::DoSavestate(Savestate* file)
FillPipeline(); FillPipeline();
} }
#endif #endif
file->VarArray(NextInstr, 2*sizeof(u32)); file->VarArray(NextInstr, 2*sizeof(u64));
file->Var32(&ExceptionBase); file->Var32(&ExceptionBase);
@ -667,7 +667,7 @@ void ARMv5::Execute()
if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>(); if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
else if (!(PU_Map[(R[15]-4)>>12] & 0x04)) [[unlikely]] // handle aborted instructions else if (CurInstr & ((u64)1<<63)) [[unlikely]] // handle aborted instructions
{ {
PrefetchAbort(); PrefetchAbort();
} }
@ -690,7 +690,7 @@ void ARMv5::Execute()
if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>(); if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
else if (!(PU_Map[(R[15]-8)>>12] & 0x04)) [[unlikely]] // handle aborted instructions else if (CurInstr & ((u64)1<<63)) [[unlikely]] // handle aborted instructions
{ {
PrefetchAbort(); PrefetchAbort();
} }

6
src/ARM.h
View File

@ -177,8 +177,8 @@ public:
u32 R_ABT[3]; u32 R_ABT[3];
u32 R_IRQ[3]; u32 R_IRQ[3];
u32 R_UND[3]; u32 R_UND[3];
u32 CurInstr; u64 CurInstr;
u32 NextInstr[2]; u64 NextInstr[2];
u32 ExceptionBase; u32 ExceptionBase;
@ -251,7 +251,7 @@ public:
void Execute(); void Execute();
// all code accesses are forced nonseq 32bit // all code accesses are forced nonseq 32bit
u32 CodeRead32(u32 addr, bool branch); u64 CodeRead32(u32 addr, bool branch);
bool DataRead8(u32 addr, u32* val) override; bool DataRead8(u32 addr, u32* val) override;
bool DataRead16(u32 addr, u32* val) override; bool DataRead16(u32 addr, u32* val) override;

2
src/ARMJIT.cpp
View File

@ -588,7 +588,7 @@ void ARMJIT::CompileBlock(ARM* cpu) noexcept
u32 numWriteAddrs = 0, writeAddrsTranslated = 0; u32 numWriteAddrs = 0, writeAddrsTranslated = 0;
cpu->FillPipeline(); cpu->FillPipeline();
u32 nextInstr[2] = {cpu->NextInstr[0], cpu->NextInstr[1]}; u32 nextInstr[2] = {(u32)cpu->NextInstr[0], (u32)cpu->NextInstr[1]};
u32 nextInstrAddr[2] = {blockAddr, r15}; u32 nextInstrAddr[2] = {blockAddr, r15};
JIT_DEBUGPRINT("start block %x %08x (%x)\n", blockAddr, cpu->CPSR, localAddr); JIT_DEBUGPRINT("start block %x %08x (%x)\n", blockAddr, cpu->CPSR, localAddr);

4
src/CP15.cpp
View File

@ -771,14 +771,14 @@ u32 ARMv5::CP15Read(u32 id) const
// TCM are handled here. // TCM are handled here.
// TODO: later on, handle PU, and maybe caches // TODO: later on, handle PU, and maybe caches
u32 ARMv5::CodeRead32(u32 addr, bool branch) u64 ARMv5::CodeRead32(u32 addr, bool branch)
{ {
// prefetch abort // prefetch abort
// the actual exception is not raised until the aborted instruction is executed // the actual exception is not raised until the aborted instruction is executed
if (!(PU_Map[addr>>12] & 0x04)) [[unlikely]] if (!(PU_Map[addr>>12] & 0x04)) [[unlikely]]
{ {
CodeCycles = 1; CodeCycles = 1;
return 0; return ((u64)1<<63);
} }
if (addr < ITCMSize) if (addr < ITCMSize)