From 5091061a39d307f9dd92ef0aa5d808fb0900121b Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Thu, 7 Nov 2024 20:16:19 -0500
Subject: [PATCH] improve accuracy of prefetch abort handling slightly

prefetch aborts should be handled on executing an instruction by a flag set when the instruction is fetched
---
 src/ARM.cpp    | 8 ++++----
 src/ARM.h      | 6 +++---
 src/ARMJIT.cpp | 2 +-
 src/CP15.cpp   | 4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/ARM.cpp b/src/ARM.cpp
index 682ce9ff..7f5d2e86 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -222,7 +222,7 @@ void ARM::DoSavestate(Savestate* file)
     file->VarArray(R_ABT, 3*sizeof(u32));
     file->VarArray(R_IRQ, 3*sizeof(u32));
     file->VarArray(R_UND, 3*sizeof(u32));
-    file->Var32(&CurInstr);
+    file->Var64(&CurInstr);
 #ifdef JIT_ENABLED
     if (file->Saving && NDS.IsJITEnabled())
     {
@@ -232,7 +232,7 @@ void ARM::DoSavestate(Savestate* file)
         FillPipeline();
     }
 #endif
-    file->VarArray(NextInstr, 2*sizeof(u32));
+    file->VarArray(NextInstr, 2*sizeof(u64));
 
     file->Var32(&ExceptionBase);
 
@@ -667,7 +667,7 @@ void ARMv5::Execute()
                 
                 
                 if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
-                else if (!(PU_Map[(R[15]-4)>>12] & 0x04)) [[unlikely]] // handle aborted instructions
+                else if (CurInstr & ((u64)1<<63)) [[unlikely]] // handle aborted instructions
                 {
                     PrefetchAbort();
                 }
@@ -690,7 +690,7 @@ void ARMv5::Execute()
                 
 
                 if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
-                else if (!(PU_Map[(R[15]-8)>>12] & 0x04)) [[unlikely]] // handle aborted instructions
+                else if (CurInstr & ((u64)1<<63)) [[unlikely]] // handle aborted instructions
                 {
                     PrefetchAbort();
                 }
diff --git a/src/ARM.h b/src/ARM.h
index e7156d72..f4b3b53f 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -177,8 +177,8 @@ public:
     u32 R_ABT[3];
     u32 R_IRQ[3];
     u32 R_UND[3];
-    u32 CurInstr;
-    u32 NextInstr[2];
+    u64 CurInstr;
+    u64 NextInstr[2];
 
     u32 ExceptionBase;
 
@@ -251,7 +251,7 @@ public:
     void Execute();
 
     // all code accesses are forced nonseq 32bit
-    u32 CodeRead32(u32 addr, bool branch);
+    u64 CodeRead32(u32 addr, bool branch);
 
     bool DataRead8(u32 addr, u32* val) override;
     bool DataRead16(u32 addr, u32* val) override;
diff --git a/src/ARMJIT.cpp b/src/ARMJIT.cpp
index 1ebcce8e..8bf509e9 100644
--- a/src/ARMJIT.cpp
+++ b/src/ARMJIT.cpp
@@ -588,7 +588,7 @@ void ARMJIT::CompileBlock(ARM* cpu) noexcept
     u32 numWriteAddrs = 0, writeAddrsTranslated = 0;
 
     cpu->FillPipeline();
-    u32 nextInstr[2] = {cpu->NextInstr[0], cpu->NextInstr[1]};
+    u32 nextInstr[2] = {(u32)cpu->NextInstr[0], (u32)cpu->NextInstr[1]};
     u32 nextInstrAddr[2] = {blockAddr, r15};
 
     JIT_DEBUGPRINT("start block %x %08x (%x)\n", blockAddr, cpu->CPSR, localAddr);
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 5bffb185..fba73bda 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -771,14 +771,14 @@ u32 ARMv5::CP15Read(u32 id) const
 // TCM are handled here.
 // TODO: later on, handle PU, and maybe caches
 
-u32 ARMv5::CodeRead32(u32 addr, bool branch)
+u64 ARMv5::CodeRead32(u32 addr, bool branch)
 {
     // prefetch abort
     // the actual exception is not raised until the aborted instruction is executed
     if (!(PU_Map[addr>>12] & 0x04)) [[unlikely]]
     {
         CodeCycles = 1;
-        return 0;
+        return ((u64)1<<63);
     }
 
     if (addr < ITCMSize)