From 1b98a3e3a0aabb32fd233832d143968cc1509a57 Mon Sep 17 00:00:00 2001
From: Arisotura <thetotalworm@gmail.com>
Date: Thu, 27 Jun 2019 14:05:51 +0200
Subject: [PATCH] fix 'shift by register' operands: always only take the lower
 8 bits of the register, fix handling for LSL/LSR >32

fixes #479
---
 src/ARMInterpreter_ALU.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/ARMInterpreter_ALU.cpp b/src/ARMInterpreter_ALU.cpp
index f23d6b2e..d60d8f87 100644
--- a/src/ARMInterpreter_ALU.cpp
+++ b/src/ARMInterpreter_ALU.cpp
@@ -106,12 +106,12 @@ namespace ARMInterpreter
     x = ROR(x, (s&0x1F));
 
 #define LSL_REG_S(x, s) \
-    if (s > 31)     { cpu->SetC(x & (1<<0));      x = 0; } \
-    else if (s > 0) { cpu->SetC(x & (1<<(32-s))); x <<= s; }
+    if (s > 31)     { cpu->SetC((s>32) ? 0 : (x & (1<<0))); x = 0; } \
+    else if (s > 0) { cpu->SetC(x & (1<<(32-s)));           x <<= s; }
 
 #define LSR_REG_S(x, s) \
-    if (s > 31)     { cpu->SetC(x & (1<<31));    x = 0; } \
-    else if (s > 0) { cpu->SetC(x & (1<<(s-1))); x >>= s; }
+    if (s > 31)     { cpu->SetC((s>32) ? 0 : (x & (1<<31))); x = 0; } \
+    else if (s > 0) { cpu->SetC(x & (1<<(s-1)));             x >>= s; }
 
 #define ASR_REG_S(x, s) \
     if (s > 31)     { cpu->SetC(x & (1<<31));    x = ((s32)x) >> 31; } \
@@ -134,7 +134,7 @@ namespace ARMInterpreter
 #define A_CALC_OP2_REG_SHIFT_REG(shiftop) \
     u32 b = cpu->R[cpu->CurInstr&0xF]; \
     if ((cpu->CurInstr&0xF)==15) b += 4; \
-    shiftop(b, cpu->R[(cpu->CurInstr>>8)&0xF]);
+    shiftop(b, (cpu->R[(cpu->CurInstr>>8)&0xF] & 0xFF));
 
 
 #define A_IMPLEMENT_ALU_OP(x,s) \