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flycast/core/deps/vixl
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Flyinghead cb8e81d473 arm64: direct memory access and jit rewrite 
generates direct vmem read & write accesses
trap sigsegv and rewrite using slow path
add w29 to allocatable registers
get rid of literals and use pc-rel branching
minor optimizations and cleanup
 		2019-01-16 13:04:16 +01:00
..
aarch32 arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
aarch64 arm64: direct memory access and jit rewrite 2019-01-16 13:04:16 +01:00
assembler-base-vixl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
code-buffer-vixl.cc arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
code-buffer-vixl.h arm64: direct memory access and jit rewrite 2019-01-16 13:04:16 +01:00
code-generation-scopes-vixl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
compiler-intrinsics-vixl.cc arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
compiler-intrinsics-vixl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
cpu-features.cc arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
cpu-features.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
globals-vixl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
invalset-vixl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
macro-assembler-interface.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
platform-vixl.h vixl: enable debug log on android 2019-01-11 15:57:37 +01:00
pool-manager-impl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
pool-manager.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
utils-vixl.cc arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
utils-vixl.h arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00